公开(公告)号：US09406752B2

公开(公告)日：2016-08-02

申请号：US14676912

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Jianwei Peng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Francis Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L21/265 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US10910471B2

公开(公告)日：2021-02-02

申请号：US16032878

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Sang Woo Lim ,  Matthew Wahlquist Stoker ,  Huang Liu ,  Jinping Liu

IPC: H01L29/76 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

公开(公告)号：US10262903B2

公开(公告)日：2019-04-16

申请号：US15630547

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.

公开(公告)号：US10224330B2

公开(公告)日：2019-03-05

申请号：US15407960

申请日：2017-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Xusheng Wu

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.

公开(公告)号：US09559176B2

公开(公告)日：2017-01-31

申请号：US15180312

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Jianwei Peng ,  Francis Benistant

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US09397162B1

公开(公告)日：2016-07-19

申请号：US14679074

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Jianwei Peng ,  Francis Benistant

IPC: H01L21/82 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L29/24

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US10784342B1

公开(公告)日：2020-09-22

申请号：US16385197

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hong Yu ,  Jianwei Peng ,  Hui Zhan

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66

Abstract: Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.

公开(公告)号：US20190131433A1

公开(公告)日：2019-05-02

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20190051735A1

公开(公告)日：2019-02-14

申请号：US15869349

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xusheng Wu ,  Jianwei Peng ,  Sipeng Gu ,  Hsien-Ching Lo

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

公开(公告)号：US10121868B1

公开(公告)日：2018-11-06

申请号：US15585865

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.