-
公开(公告)号：US20160247821A1
公开(公告)日：2016-08-25
申请号：US14388182
申请日：2013-10-31
IPC: H01L27/12
CPC classification number: H01L27/124 , G02F1/136286 , G02F1/1368 , G02F2001/134372 , H01L27/1222 , H01L27/1288 , H01L29/78642
Abstract: An array substrate including: a base substrate and a thin film transistor unit provided on the base substrate; the thin film transistor unit comprises: a first gate electrode provided on the base substrate, a gate insulating layer provided on the first gate electrode, a source electrode disposed in a same layer as the first gate electrode, an active layer provided on the source electrode, a drain electrode provided on the active layer, and the gate insulating layer disposed between the first gate electrode and the source electrode. This array substrate reduces a channel length of a conducting channel of the thin film transistor unit, and meanwhile increases an aperture ratio of a pixel.
Abstract translation: 一种阵列基板，包括：基底基板和设置在基底基板上的薄膜晶体管单元; 所述薄膜晶体管单元包括：设置在所述基底基板上的第一栅极电极，设置在所述第一栅电极上的栅极绝缘层，与所述第一栅电极设置在同一层中的源电极，设置在所述源极上的有源层 设置在有源层上的漏电极，以及设置在第一栅电极和源电极之间的栅极绝缘层。 该阵列基板减小了薄膜晶体管单元的导电沟道的沟道长度，同时增加了像素的开口率。
-
公开(公告)号：US20230296942A1
公开(公告)日：2023-09-21
申请号：US17441272
申请日：2020-12-11
Inventor： Wei REN , Wei LI , Yanfeng LI , Haoyi XIN , Jing LI , Jingjing XU , Chenrong QIAO , Yanyong SONG , Xu QIAO , Rula SHA , Min ZHANG
IPC: G02F1/1343 , G02F1/1345
CPC classification number: G02F1/134309 , G02F1/13439 , G02F1/13454
Abstract: A pixel electrode, including: a plurality of strip-shaped first electrodes, where the plurality of the first electrodes are arranged along a first direction, each of the first electrodes extends along a second direction, and the second direction intersects with the first direction; a second electrode, where the second electrode is connected to first ends of the plurality of first electrodes, and the first ends of the plurality of first electrodes are connected through the second electrode; and a third electrode, where the third electrode is connected to a second end of at least one of the first electrodes, and a direction of an electric field of an area in which the third electrode is disposed intersects with both the first direction and the second direction.
-
公开(公告)号：US20230022752A1
公开(公告)日：2023-01-26
申请号：US17041544
申请日：2019-11-13
Inventor： Xiaohe SHEN , Chungen YUAN , Haochen CUI , Lijiao Hu , Tao HU , Jing LI , Weiqiong GAN
IPC: B01L3/00
Abstract: A detection chip is disclosed. The detection chip includes a sample injection structure, a filter structure, and a reaction structure which are sequentially connected. The filter structure includes a first main body, and a first inlet portion and a first outlet portion respectively on two sides of the first main body. A width of the first inlet portion gradually decreases in a direction away from the first main body, and a width of the first outlet portion gradually decreases in a direction away from the first main body.
-
Patent Agency Ranking
24.发明申请公开(公告)号：US20210215981A1
公开(公告)日：2021-07-15
申请号：US16954006
申请日：2020-01-09
IPC: G02F1/1362 , H01L27/12 , G02F1/1335 , G02F1/1368 , G02F1/1333 , G02F1/1343
Abstract: Disclosed are an array substrate and a method for manufacturing the same, a display panel, and a display device. The array substrate includes: a base substrate; a TFT array layer provided on the base substrate, wherein the TFT array layer includes a plurality of driver transistors arranged in an array; a color resist layer provided on a side of the TFT array layer distal to the base substrate, wherein the color resist layer includes a plurality of color resist patterns independent from each other, a first opening is formed between adjacent ones of the color resist patterns, and an orthogonal projection of the first opening onto the base substrate at least partially overlaps with an orthogonal projection of an output electrode in a respective one of the driver transistors onto the base substrate; and pixel electrodes provided on a side of the color resist layer distal to the base substrate.
-
公开(公告)号：US20190120266A1
公开(公告)日：2019-04-25
申请号：US15937013
申请日：2018-03-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jing LI
Abstract: The present disclosure provides a fixing device, a display module, and a display device. The fixing device includes a frame and a fixture for fixing a display module, a protrusion is provided at a side edge of the frame, and a through-hole is provided in the protrusion, the fixture is detachably connected with the through-hole, and the fixture has a connecting hole along an axial direction of the fixture, the connecting hole is used for detachably connecting with a connecting member. The fixing device provided in the present disclosure can not only satisfy the appearance effect of a narrow frame, but also can achieve the fixing of the display module during assembly.
-
26.发明申请公开(公告)号：US20170287950A1
公开(公告)日：2017-10-05
申请号：US15625436
申请日：2017-06-16
Inventor： Zhenyu XIE , Shaoying XU , Tiansheng LI , Changjiang YAN , Jing LI , Zongmin TIAN
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1248 , H01L27/1225 , H01L29/66969 , H01L29/78606 , H01L29/7869
Abstract: The technical disclosure relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a base substrate, a gate electrode, an active layer, source/drain electrodes, a pixel electrode and one or more insulating layers, wherein at least one of the insulating layers comprises a bottom insulating sub-layer and a top insulating sub-layer, the top insulating sub-layer having a hydrogen content higher than that of the bottom insulating sub-layer.
-
公开(公告)号：US20160372489A1
公开(公告)日：2016-12-22
申请号：US14905380
申请日：2015-08-18
IPC: H01L27/12 , H01L25/00 , H01L21/768 , H01L25/065 , H01L21/02
CPC classification number: H01L27/124 , H01L21/02271 , H01L21/76802 , H01L21/76804 , H01L21/76816 , H01L25/0655 , H01L25/50 , H01L27/1259
Abstract: The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.
Abstract translation: 本发明提供一种显示面板及其制造方法以及显示装置。 显示面板包括像素区域和扇出区域，第一信号线和第二信号线被设置为在像素区域中彼此相交并分别延伸到扇出区域中，第一绝缘层设置在 第一信号线和第二信号线，第二绝缘层设置在第二信号线上，第二绝缘层包括至少四层结构，并且第二绝缘层的每层结构的密度逐渐降低 远离第一绝缘层的方向。 通过蚀刻形成在第二绝缘层中的通孔的尺寸小于现有技术中形成的通孔的尺寸。
-
28.发明申请FABRICATING METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR AND DISPLAY PANEL 有权薄膜晶体管，薄膜晶体管和显示面板的制作方法公开(公告)号：US20160035901A1
公开(公告)日：2016-02-04
申请号：US14421931
申请日：2014-04-25
Inventor： Jing LI , Zhenyu XIE , Xu CHEN , Wenyu ZHANG , Da XU
IPC: H01L29/786 , H01L29/66 , H01L21/311 , H01L21/02
CPC classification number: H01L29/78675 , H01L21/0217 , H01L21/02532 , H01L21/02592 , H01L21/02672 , H01L21/31111 , H01L27/1281 , H01L29/66757 , H01L29/78603
Abstract: Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon. The fabricating method a thin film transistor comprises following M1, depositing an inducing layer on a substrate; M2, etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape; M3, depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and the polycrystalline silicone layer and the inducing layer together forming a semiconductor layer; and M4, forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer.
Abstract translation: 本发明的实施例提供薄膜晶体管，薄膜晶体管和显示面板的制造方法，以便提高多晶硅中的载流子迁移率。 制造方法薄膜晶体管包括以下M1，在衬底上沉积诱导层; M2，通过蚀刻处理蚀刻诱导层中的凹部，凹部具有规定形状的边缘; M3，在具有规定形状的边缘的凹部中沉积非晶硅层，并且通过结晶法诱导非晶硅层形成多晶硅层，多晶硅层中的多晶硅晶粒沿垂直于边缘的方向排列 通过限制凹部的边缘，并且多晶硅层和诱导层一起形成半导体层; 和M4，在半导体层上依次形成栅极绝缘层，栅极，钝化层以及与半导体层连接的源极和漏极。
-
-
-
-
-
-
-
Search Results
28
records
(took 0.019 seconds)
