公开(公告)号：US20240405124A1

公开(公告)日：2024-12-05

申请号：US18327200

申请日：2023-06-01

Applicant: Allegro MicroSystems, LLC

Inventor： Yu-Chun Li ,  Thomas S. Chung ,  Maxim Klebanov ,  Chung C. Kuo ,  James M. McClay ,  Robert A. Wilson

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: According to one aspect of the present disclosure, a semiconductor device includes a substrate having a first type dopant. In some embodiments, the semiconductor device also includes an epitaxial layer above the substrate, having a second type dopant and a top region. In some embodiments, the semiconductor device also includes a trench in the top region of the epitaxial layer; at least one doped ring implanted in the epitaxial layer below the trench; and a dielectric material filling within the trench. In some embodiments, there is a twelve-sided body tie in the epitaxial layer, wherein the sides of the twelve-sided body tie are not all equal to each other.

公开(公告)号：US20240170478A1

公开(公告)日：2024-05-23

申请号：US18058318

申请日：2022-11-23

Applicant: Allegro MicroSystems, LLC

Inventor： Chung C. Kuo ,  Maxim Klebanov ,  James McClay ,  Sagar Saxena

IPC: H01L27/02

CPC classification number: H01L27/0274

Abstract: In one aspect, a semiconductor device includes a first region, a second region and a trench separating the first and the second regions. The trench includes a trench liner that includes a dielectric, and a semiconductor material surrounded by the trench liner. The first region includes a first buried layer implanted in a substrate, a first stack of layers that includes a first middle layer located above the first buried layer, a first well located on and in contact with the first middle layer and a second well in contact with the first well. The second region includes a second stack of layers. In response to a voltage difference between the first and the second regions exceeding a threshold voltage, a conduction current is formed. A distance of the first stack of layers to the trench controls the conduction current to activate a transistor to function as a voltage clamp.

公开(公告)号：US20240074322A1

公开(公告)日：2024-02-29

申请号：US17823461

申请日：2022-08-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Yen Ting Liu ,  Sundar Chetlur ,  Paolo Campiglio ,  Samridh Jaiswal

IPC: H01L43/12 ,  G01R33/00 ,  H01F41/34

CPC classification number: H01L43/12 ,  G01R33/0052 ,  H01F41/34 ,  H01L43/02

Abstract: In one aspect, a method includes depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure; depositing a first hard mask on the MR layers; depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask; etching the exposed portions of the first hard mask; etching a portion of the MR layers using the first hard mask; depositing a second hard mask on a first capping layer; depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask; etching the exposed portions of the second hard mask; etching the MR element using the second hard mask; etching portions of the first hard mask down to a top MR layer of the MR element; and depositing a conducting material on the top MR layer to form an electroconductive contact.

公开(公告)号：US20230361223A1

公开(公告)日：2023-11-09

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US20230253507A1

公开(公告)日：2023-08-10

申请号：US17650418

申请日：2022-02-09

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Maxim Klebanov ,  Sundar Chetlur ,  James McClay

IPC: H01L29/788 ,  H01L29/08 ,  H01L29/66 ,  G11C16/10 ,  G11C16/14

CPC classification number: H01L29/7883 ,  G11C16/10 ,  G11C16/14 ,  H01L29/0847 ,  H01L29/66825

Abstract: In one aspect, a flash memory cell includes a well having a first-type dopant, a source having a second-type dopant and formed within the well, a drain having the second-type dopant and formed within the well, a floating gate above the well, a control gate above the floating gate, an oxide compound disposed between the floating gate and the control gate, and a tunnel oxide disposed between the floating gate and the well. The flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate. The flash memory cell is configured, in the other one of the program or the erase mode, to move an electron is from the floating gate to the drain.

公开(公告)号：US11367830B2

公开(公告)日：2022-06-21

申请号：US17014129

申请日：2020-09-08

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Paolo Campiglio ,  Yen Ting Liu

IPC: H01L43/02 ,  G01R33/09 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.

公开(公告)号：US20220115316A1

公开(公告)日：2022-04-14

申请号：US17067178

申请日：2020-10-09

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/522 ,  H01L21/8234

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

公开(公告)号：US11112230B2

公开(公告)日：2021-09-07

申请号：US16282539

申请日：2019-02-22

Applicant: Allegro MicroSystems, LLC

Inventor： Alexander Latham ,  Maxim Klebanov

IPC: G01B7/30 ,  G01D5/20 ,  G01R33/00 ,  G01R33/028 ,  G01R33/06

Abstract: Methods and apparatus for a sensor with a main coil to direct a magnetic field at a rotating target for inducing eddy currents in an end of the target and a sensing element to detect a magnetic field reflected from the target, wherein the target end comprises a conductive surface. The reflected magnetic field can be processed to determine an angular position of the target.

公开(公告)号：US10916438B2

公开(公告)日：2021-02-09

申请号：US16407500

申请日：2019-05-09

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Sundar Chetlur ,  James McClay

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/308 ,  H01L21/033 ,  H01L29/51

Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.

公开(公告)号：US20200076189A1

公开(公告)日：2020-03-05

申请号：US16115901

申请日：2018-08-29

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H02H9/04 ,  H02H1/00

Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.