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    Clock data recovery circuitry with programmable clock phase selection
    21.
    发明授权
    Clock data recovery circuitry with programmable clock phase selection 有权
    具有可编程时钟相位选择的时钟数据恢复电路

    公开(公告)号：US09112655B1

    公开(公告)日：2015-08-18

    申请号：US13954751

    申请日：2013-07-30

    Applicant: Altera Corporation

    Inventor： Tim Tri Hoang ,  Weiqi Ding ,  Sangeeta Raman ,  Richard Hernandez

    IPC: H04L25/38 ,  H04L7/00

    CPC classification number: H03L7/0807 ,  H03L7/087 ,  H04L1/20 ,  H04L7/0025 ,  H04L7/033

    Abstract: Integrated circuits with high-speed communications capabilities are provided. Such types of integrated circuits may include clock data recovery (CDR) circuitry. The CDR circuitry may receive incoming data and may generate multiple clock signals that are used to latch the incoming data. The CDR circuitry may include data latching circuitry for separately latching even and odd data bits in alternating clock cycles. In particular, the data latching circuitry may be controlled using first, second, third, and fourth clock signals having different respective phase settings. The first and second clock signals may be used to capture even and odd data bits, respectively. The third and fourth clock signals may be used to sample data near the transition between the even and odd data bits. The phase of the first and second clock signals may be dynamically adjusted. The phase setting that yields the optimal link performance may be selected for normal operation.

    Abstract translation: 提供了具有高速通信能力的集成电路。 这种类型的集成电路可以包括时钟数据恢复（CDR）电路。 CDR电路可以接收输入数据并且可以生成用于锁存输入数据的多个时钟信号。 CDR电路可以包括数据锁存电路，用于在交替的时钟周期中分别锁存偶数和奇数数据位。 特别地，可以使用具有不同相应相位设置的第一，第二，第三和第四时钟信号来控制数据锁存电路。 第一和第二时钟信号可分别用于捕获偶数和奇数数据位。 第三和第四时钟信号可用于在偶数和奇数数据位之间的转换附近采样数据。 可以动态地调整第一和第二时钟信号的相位。 可以选择产生最佳链路性能的相位设置用于正常操作。

    High-speed serial data signal receiver circuitry
    22.
    发明授权
    High-speed serial data signal receiver circuitry 有权

    公开(公告)号：US09960937B2

    公开(公告)日：2018-05-01

    申请号：US15495622

    申请日：2017-04-24

    Applicant: Altera Corporation

    Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Y. Shumarayev

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

    HIGH-SPEED SERIAL DATA SIGNAL RECEIVER CIRCUITRY
    23.
    发明申请
    HIGH-SPEED SERIAL DATA SIGNAL RECEIVER CIRCUITRY 审中-公开

    公开(公告)号：US20170230209A1

    公开(公告)日：2017-08-10

    申请号：US15495622

    申请日：2017-04-24

    Applicant: Altera Corporation

    Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Y. Shumarayev

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

    High-speed serial data signal receiver circuitry
    24.
    发明授权
    High-speed serial data signal receiver circuitry 有权

    公开(公告)号：US09660846B2

    公开(公告)日：2017-05-23

    申请号：US14633080

    申请日：2015-02-26

    Applicant: Altera Corporation

    Inventor： Weiqi Ding ,  Mengchi Lui ,  Wilson Wong ,  Sergey Y. Shumarayev

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

    Phase-locked loop architecture and clock distribution system
    25.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US09350530B1

    公开(公告)日：2016-05-24

    申请号：US14487867

    申请日：2014-09-16

    Applicant: ALTERA CORPORATION

    Inventor： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding

    IPC: H03L7/06 ,  H04L7/033

    CPC classification number: H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    Abstract: One embodiment relates to an integrated circuit including multiple PMA modules, a plurality of multiple-purpose PLLs, multiple reference clock signal inputs, and a programmable clock network. Each PMA module includes multiple CDR circuits, receives multiple serial data signals, and outputs data from those signals in parallel form. The programmable clock network allows the reference clock signals to be selectively shared by the PMA modules and the multiple-purpose PLLs. Another embodiment relates to a method of providing clock signals for multiple purposes in an integrated circuit. Clock signals are generated by a plurality of multiple-purpose PLLs and are selectively distributed to PMA modules arranged at a side of the integrated circuit and to logic circuitry arranged in a core section of the integrated circuit. The clock signals are used by circuitry in the PMA modules for supporting a plurality of data communications channels. Other embodiments and features are also disclosed.

    Abstract translation: 一个实施例涉及包括多个PMA模块，多个多用途PLL，多个参考时钟信号输入和可编程时钟网络的集成电路。 每个PMA模块包括多个CDR电路，接收多个串行数据信号，并以并行形式从这些信号中输出数据。 可编程时钟网络允许参考时钟信号由PMA模块和多用途PLL选择性共享。 另一实施例涉及在集成电路中为多个目的提供时钟信号的方法。 时钟信号由多个多用途PLL产生，并且选择性地分配到布置在集成电路侧的PMA模块和布置在集成电路的核心部分中的逻辑电路。 时钟信号由PMA模块中的电路用于支持多个数据通信信道。 还公开了其它实施例和特征。

    Methods and apparatus for multiple-stage CTLE adaptation
    26.
    发明授权
    Methods and apparatus for multiple-stage CTLE adaptation 有权
    多阶段CTLE适应方法与装置

    公开(公告)号：US09172566B1

    公开(公告)日：2015-10-27

    申请号：US14057945

    申请日：2013-10-18

    Applicant: ALTERA CORPORATION

    Inventor： Wei Li ,  Weiqi Ding ,  Wilson Wong ,  Jie Shen ,  Xudong Shi

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03885

    Abstract: A method of equalizing an input data signal using a multiple-stage continuous-time linear equalization (CTLE) circuit. A zero-forcing least-mean-square (ZF LMS) procedure is applied to adapt the settings of the CTLE stages. The amplitude settings and the frequency boost settings of the CTLE stages are adapted within the ZF LMS procedure. In an exemplary implementation, an error screening threshold may be applied to an error signal within the ZF LMS procedure to generate a reduced error signal such that weight updates do not occur if the error signal is below the error screening threshold. In addition, if an accumulated sign error signal within the ZF LMS procedure reaches a predetermined maximum indicative of a high loss channel, then a setting for a variable gain amplifier may be increased, and an amplitude setting for the CTLE circuit may be decreased. Other embodiments, aspects and features are also disclosed.

    Abstract translation: 一种使用多级连续时间线性均衡（CTLE）电路来均衡输入数据信号的方法。 应用零强制最小均方（ZF LMS）程序来适应CTLE阶段的设置。 在ZF LMS过程中，CTLE阶段的幅度设置和频率提升设置进行了调整。 在示例性实现中，误差屏蔽阈值可以应用于ZF LMS过程中的误差信号以产生减小的误差信号，使得如果误差信号低于误码筛选阈值，则不发生加权更新。 此外，如果在ZF LMS程序内累积的符号误差信号达到指示高损耗信道的预定最大值，则可增加可变增益放大器的设置，并且可以减小CTLE电路的振幅设置。 还公开了其它实施例，方面和特征。

    Input-output circuitry for integrated circuits
    27.
    发明授权
    Input-output circuitry for integrated circuits 有权
    集成电路的输入输出电路

    公开(公告)号：US09106230B1

    公开(公告)日：2015-08-11

    申请号：US13828467

    申请日：2013-03-14

    Applicant: Altera Corporation

    Inventor： Bonnie I. Wang ,  Warren Nordyke ,  Weiqi Ding ,  Yan Chong

    IPC: H03L7/06 ,  H03K19/173

    CPC classification number: H03K19/1737

    Abstract: An integrated such as a programmable integrated circuit may include input-output pins that have associated input-output circuits. An input-output circuit may include memory interface circuits, clock recovery interface circuits, shared interpolator circuitry, and selection circuitry that may be configured to convey control signals from selected interface circuits to the shared interpolator circuitry. The interpolator circuitry may receive multiple clock signals and perform phase interpolation operations on the clock signals based on the selected control signals to produce modified clock signals. The modified clock signals may be used by the selected interface circuits for communications over the input-output pins. Logic design computing equipment such as computing equipment having CAD tools may be used to configure the selection circuitry.

    Abstract translation: 诸如可编程集成电路的集成可以包括具有相关联的输入 - 输出电路的输入 - 输出引脚。 输入 - 输出电路可以包括存储器接口电路，时钟恢复接口电路，共享内插器电路和可被配置为将控制信号从选择的接口电路传送到共享内插器电路的选择电路。 内插器电路可以接收多个时钟信号，并且基于所选择的控制信号对时钟信号执行相位插值操作，以产生修改的时钟信号。 所修改的时钟信号可以被所选择的接口电路用于通过输入输出引脚进行通信。 诸如具有CAD工具的计算设备的逻辑设计计算设备可以用于配置选择电路。

    Programmable high-speed voltage-mode differential driver
    28.
    发明授权
    Programmable high-speed voltage-mode differential driver 有权
    可编程高速电压模式差分驱动器

    公开(公告)号：US09065399B2

    公开(公告)日：2015-06-23

    申请号：US13918480

    申请日：2013-06-14

    Applicant: ALTERA CORPORATION

    Inventor： Bonnie I. Wang ,  Weiqi Ding ,  Tim Tri Hoang ,  Richard Hernandez ,  Haidang Lin

    IPC: H03F3/45 ,  H04L25/02 ,  H03K19/0185

    CPC classification number: H03F3/45071 ,  H03K19/018514 ,  H03K19/018585 ,  H04L25/0272

    Abstract: A voltage-mode differential driver is disclosed. The differential driver includes two driver arms, each driver arm including a variable-impedance driver for driving a single-ended output signal. Each variable-impedance driver comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

    Abstract translation: 公开了一种电压模式差分驱动器。 差分驱动器包括两个驱动器臂，每个驱动臂包括用于驱动单端输出信号的可变阻抗驱动器。 每个可变阻抗驱动器包括多个驱动器片，其中每个驱动器片包括预驱动器电路和驱动器电路。 有利地，已经确定所公开的电压模式驱动器设计需要比常规电流模式驱动器更少的功率。 在一个实现中，所公开的电压模式驱动器设计提供独立编程两个单端输出的延迟的能力，以便补偿差分偏移。 还公开了其它实施例和特征。

    Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter
    29.
    发明授权
    Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter 有权
    逐次逼近寄存器模数转换器的数字校准系统和方法

    公开(公告)号：US09054721B1

    公开(公告)日：2015-06-09

    申请号：US14180115

    申请日：2014-02-13

    Applicant: Altera Corporation

    Inventor： Wei Li ,  Weiqi Ding ,  Yanjing Ke

    IPC: H03M1/10 ,  H03M1/12 ,  H03M1/80 ,  H03M1/00

    CPC classification number: H03M1/1009 ,  H03M1/00 ,  H03M1/10 ,  H03M1/1061 ,  H03M1/12 ,  H03M1/38 ,  H03M1/804

    Abstract: Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

    Abstract translation: 公开了校准逐次逼近寄存器模数转换器（ADC）的系统和方法。 多个电容器级，第一电容器阵列和第一电容器级并联耦合。 将第一电容器级的电容与多个电容器级和第一电容器阵列的电容之和进行比较。 响应于比较，如果第一电容器级的电容小于多个电容器级的电容和第一电容器级的电容之和，则通过增加第二电容器阵列的电容来增加第一电容器级的电容 电容阵列。

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