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    Semiconductor device and manufacturing method thereof
    26.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07906833B2

    公开(公告)日：2011-03-15

    申请号：US12273901

    申请日：2008-11-19

    申请人： Takaharu Yamano ,  Yoshihiro Machida

    发明人： Takaharu Yamano ,  Yoshihiro Machida

    IPC分类号： H01L23/544

    CPC分类号： H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/10 ,  H01L2224/02333 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014

    摘要： A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.

    摘要翻译： 一种制造半导体器件的方法，具有制备具有多个半导体芯片形成区域的半导体衬底和布置在多个半导体芯片形成区域之间并包括衬底切割位置的划线区域的准备步骤，半导体芯片形成步骤 在所述多个半导体芯片形成区域上形成具有电极焊盘的半导体芯片，在所述半导体芯片上形成第一绝缘层和所述半导体基板的划线区域的第一绝缘层形成步骤，形成第二绝缘层形成工序， 除了与基板切断位置对应的区域之外的第一绝缘层上的绝缘层，以及在基板切断位置切断半导体基板的切断工序。

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    27.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号：US20110003433A1

    公开(公告)日：2011-01-06

    申请号：US12819379

    申请日：2010-06-21

    申请人： Yoichi HARAYAMA ,  Takaharu Yamano

    发明人： Yoichi HARAYAMA ,  Takaharu Yamano

    IPC分类号： H01L21/50

    CPC分类号： H01L21/561 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02333 ,  H01L2224/94 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/11

    摘要： A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separate into individual semiconductor devices.

    摘要翻译： 所公开的装置包括半导体器件的制造方法，其包括制备半导体衬底形成区域，围绕这些区域的划线区域以及形成在划线区域中并且比划线区域窄的切割区域的半导体衬底，形成校验图案和半导体芯片，形成 抗蚀剂膜，通过比划线区域窄的槽形成，并且比检查图案和切割区域宽，通过使用抗蚀剂膜的湿吹工艺去除检查图案，并在保护膜和半导体基板的部分共同形成槽 形成布线形成面，通过除去直到连接面露出，形成布线图案，切割半导体基板，绝缘层，绝缘层 树脂层和焊料 抗蚀剂层分离成单独的半导体器件。

    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
    30.
    发明申请
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 有权
    半导体器件及其制造方法

    公开(公告)号：US20090321896A1

    公开(公告)日：2009-12-31

    申请号：US12489577

    申请日：2009-06-23

    申请人： Takaharu YAMANO

    发明人： Takaharu YAMANO

    IPC分类号： H01L23/552 ,  H01L21/50

    CPC分类号： H01L23/522 ,  H01L23/3114 ,  H01L23/552 ,  H01L23/556 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13021 ,  H01L2224/94 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2224/11

    摘要： There is provided a semiconductor device 10 including a solder resist 16 for protecting a wiring pattern 14 electrically connected to a semiconductor chip 11 via an internal connection terminal 12, characterized in that the solder resist 16 is arranged to cover the upper surface of the portion of the wiring pattern 14 not corresponding to the arrangement region of the external connection terminal 17 and the side surface 14B of the wiring pattern 14 and that the area of the solder resist 16 assumed when the upper surface 13A of an insulation layer 13 is viewed from above is substantially the same as that of the wiring pattern 14 assumed when the upper surface 13A of the insulation layer 13 is viewed from above.

    摘要翻译： 提供了一种半导体器件10，其包括用于保护经由内部连接端子12电连接到半导体芯片11的布线图案14的阻焊剂16，其特征在于，阻焊剂16布置成覆盖部分的上表面 布线图案14不对应于外部连接端子17的布置区域和布线图案14的侧面14B，并且当从上方观察绝缘层13的上表面13A时假定阻焊层16的面积 与当从上方观察绝缘层13的上表面13A时假设的布线图案14基本相同。