公开(公告)号：US07082055B2

公开(公告)日：2006-07-25

申请号：US11108634

申请日：2005-04-19

Applicant: Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

Inventor： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

IPC: G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

公开(公告)号：US20060120159A1

公开(公告)日：2006-06-08

申请号：US11337653

申请日：2006-01-24

Applicant: Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

Inventor： Makoto Sakuma ,  Fumitaka Arai ,  Riichiro Shirota ,  Yasuhiko Matsunaga

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.

Abstract translation: 半导体存储器具有存储单元矩阵，其包括沿着行方向交替排列的多个第一和第二单元列，每个单元列由多个存储单元晶体管实现，并且外围电路被配置为驱动存储单元矩阵， 从存储单元矩阵读取信息。 外围电路包括（a）被配置为将第一数据写入第一单元列中的存储单元晶体管的引导程序电路，（b）滞后程序电路，被配置为将第二数据写入第一单元列之后的第二单元列中的存储单元晶体管 写入数据，以及（c）被配置为控制第一单元列的存储单元晶体管的阈值电压的变化的电压控制器。

公开(公告)号：US07049653B2

公开(公告)日：2006-05-23

申请号：US11168410

申请日：2005-06-29

Applicant: Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

Inventor： Michiharu Matsui ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

Abstract: A semiconductor device of a selective gate region having a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating film, and an element isolating region including an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer. The element isolating region isolates an element region and is self-aligned with the first electrode layer, a second insulating film is formed on the first electrode layer and the element isolating region, and an open portion exposes a surface of the first electrode layer and is formed in the second insulating film. A second electrode layer is formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

Abstract translation: 具有半导体层的选择性栅极区域的半导体器件，形成在半导体层上的第一绝缘膜，形成在第一绝缘膜上的第一电极层，以及包括元件隔离绝缘膜的元件隔离区域，所述元件隔离绝缘膜形成为延伸穿过 第一电极层和第一绝缘膜到达半导体层的内部区域。 元件隔离区域隔离元件区域并且与第一电极层自对准，第二绝缘膜形成在第一电极层和元件隔离区域上，开放部分露出第一电极层的表面，并且是 形成在第二绝缘膜中。 第二电极层形成在第二绝缘膜和第一电极层的暴露表面上，第二电极层经由开口部分电连接到第一电极层。

公开(公告)号：US20060071293A1

公开(公告)日：2006-04-06

申请号：US11283742

申请日：2005-11-22

Applicant: Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

Inventor： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC: H01L29/00

CPC classification number: H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

Abstract: An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

公开(公告)号：US20050281087A1

公开(公告)日：2005-12-22

申请号：US11211633

申请日：2005-08-26

Applicant: Riichiro Shirota ,  Kikuko Sugimae

Inventor： Riichiro Shirota ,  Kikuko Sugimae

IPC: G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L31/109

CPC classification number: H01L27/11526 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11558

Abstract: A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.

Abstract translation: 存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。 位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。 单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。 源极线连接到单元晶体管的源极区域。

公开(公告)号：US20050224894A1

公开(公告)日：2005-10-13

申请号：US11108634

申请日：2005-04-19

Applicant: Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

Inventor： Masayuki Ichige ,  Riichiro Shirota ,  Kikuko Sugimae

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/94

CPC classification number: H01L27/11521 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

Abstract translation: 半导体集成电路器件包括半导体衬底，元件隔离区，第一互连，第二互连和连接在第一互连和第二互连中的相应一个之间的存储单元单元。 存储单元单元包括不大于2的选择晶体管和存储单元晶体管。 存储单元晶体管连接在两个选择晶体管之间。 存储单元晶体管具有电荷存储层，该电荷存储层的侧表面位于与元件隔离区的侧表面相同的平面或基本上相同的平面中。

公开(公告)号：US06859394B2

公开(公告)日：2005-02-22

申请号：US10090995

申请日：2002-03-06

Applicant: Yasuhiko Matsunaga ,  Toshitake Yaegashi ,  Fumitaka Arai ,  Riichiro Shirota

Inventor： Yasuhiko Matsunaga ,  Toshitake Yaegashi ,  Fumitaka Arai ,  Riichiro Shirota

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bit line BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.

Abstract translation: 具有写入模式的非易失性半导体存储器件，其中可以可靠地防止写入错误。 存储装置包括NAND单元，其包括串联连接的多个存储晶体管，并且一端经选择栅极晶体管CG1连接到位线BL，另一端经由选择栅极晶体管SG2连接到公共源极线SL 。 写入电压Vpgm被施加到NAND单元中所选择的存储晶体管的控制栅极，并且Vss被施加到与所选存储晶体管相邻的非选择存储晶体管的控制栅极，从而将数据写入选择存储晶体管。 当在写入操作中选择来自位线BL侧的第二存储晶体管时，中间电压Vpass从位线BL侧施加到第一未选择的存储晶体管的控制栅极，施加中等电压Vpass 从位线BL侧到第三和随后的未选择的存储器晶体管的控制栅极。

公开(公告)号：US06845042B2

公开(公告)日：2005-01-18

申请号：US10359216

申请日：2003-02-06

Applicant: Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

Inventor： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC: G11C16/00 ,  G06K17/00 ,  G06K19/077 ,  G11C11/34 ,  G11C14/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

Abstract translation: 一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

公开(公告)号：US06828627B2

公开(公告)日：2004-12-07

申请号：US10742952

申请日：2003-12-23

Applicant: Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

Inventor： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC: H01L2972

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract translation: 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

公开(公告)号：US06703669B1

公开(公告)日：2004-03-09

申请号：US09714228

申请日：2000-11-17

Applicant: Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

Inventor： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

Abstract translation: 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。