公开(公告)号：US20080215822A1

公开(公告)日：2008-09-04

申请号：US11933178

申请日：2007-10-31

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20190196573A1

公开(公告)日：2019-06-27

申请号：US15849995

申请日：2017-12-21

申请人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

发明人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/28

CPC分类号： G06F1/3293 ,  G06F1/28

摘要： In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.

公开(公告)号：US20180039322A1

公开(公告)日：2018-02-08

申请号：US15227040

申请日：2016-08-03

申请人： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

发明人： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

摘要： In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

公开(公告)号：US20170371399A1

公开(公告)日：2017-12-28

申请号：US15190377

申请日：2016-06-23

申请人： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

发明人： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

IPC分类号： G06F1/32 ,  G06F13/24 ,  G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/266 ,  G06F13/24 ,  Y02D10/14

摘要： In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20160335090A1

公开(公告)日：2016-11-17

申请号：US15221557

申请日：2016-07-27

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F9/38 ,  G06F12/1027 ,  G06F12/0875

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US09026829B2

公开(公告)日：2015-05-05

申请号：US12890652

申请日：2010-09-25

申请人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

发明人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3203 ,  G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

摘要翻译： 描述了优化封装级功率状态使用的方法和设备。 在一个实施例中，处理器控制逻辑接收到进入较低功耗状态（诸如封装级更深的睡眠状态）的请求。 控制逻辑确定进入较低功耗状态的最后一个入口与当前时间之间的时差或增量。 然后，控制逻辑基于时间差与对应于较低功耗状态的阈值的比较，引起最后一级高速缓冲存储器的刷新。 还要求和公开其它实施例。

公开(公告)号：US20140380076A1

公开(公告)日：2014-12-25

申请号：US13926025

申请日：2013-06-25

申请人： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

发明人： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3243 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152

摘要： In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元（PCU），以控制处理器的功率消耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能标度值，并且至少部分地基于性能标度值来计算动态性能 - 频率映射。 描述和要求保护其他实施例。

公开(公告)号：US20140344815A1

公开(公告)日：2014-11-20

申请号：US13993273

申请日：2012-03-30

申请人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Ehud Cohen

发明人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Ehud Cohen

IPC分类号： G06F9/48

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/461 ,  G06F9/485

摘要： An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.

摘要翻译： 描述了具有多个芯的装置，每个芯具有：a）加速器; 和b）耦合到加速器的通用CPU。 通用CPU具有功能单元逻辑电路，以执行返回一定量的存储空间以存储加速器的上下文信息的指令。

公开(公告)号：US20140317430A1

公开(公告)日：2014-10-23

申请号：US14317239

申请日：2014-06-27

申请人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

发明人： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

摘要： A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

摘要翻译： 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

公开(公告)号：US20140304488A1

公开(公告)日：2014-10-09

申请号：US14312669

申请日：2014-06-23

申请人： Ohad Falik ,  Ben-Zion Friedman ,  Jack Doweck ,  Eliezer Weissmann ,  James B. Crossland

发明人： Ohad Falik ,  Ben-Zion Friedman ,  Jack Doweck ,  Eliezer Weissmann ,  James B. Crossland

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.