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公开(公告)号：US20230421140A1
公开(公告)日：2023-12-28
申请号：US18331495
申请日：2023-06-08
申请人： ROHM CO., LTD.
发明人： Hisashi SUGIE
IPC分类号： H03K3/03 , H03K19/0185 , H03K3/011
CPC分类号： H03K3/0307 , H03K19/018521 , H03K3/011
摘要： A first current source charges a capacitor. A second current source supplies a current to an input node of an inverter. A current mirror circuit has its output node coupled to an input node of the inverter. A resistor is coupled between the input node of the current mirror circuit and the capacitor.
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公开(公告)号：US11843381B2
公开(公告)日：2023-12-12
申请号：US18085862
申请日：2022-12-21
发明人： Athos Canclini , Mario Dellea , Can Baltaci , Clement Cheung
IPC分类号： H03K3/03 , H03K17/687 , H03K3/013 , H03K3/011
CPC分类号： H03K3/0315 , H03K3/011 , H03K3/013 , H03K17/6874
摘要： According to an aspect of the disclosure a ring-oscillator control circuit includes a voltage reference, a ring oscillator, a power supply and a supply controller. The supply controller may be configured to select the power supply among an energy storage and an energy source such as to supply the ring oscillator in function of the voltage reference.
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公开(公告)号：US20230387923A1
公开(公告)日：2023-11-30
申请号：US18366742
申请日：2023-08-08
CPC分类号： H03L7/0995 , H03K3/013 , H03K3/0322
摘要： Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.
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公开(公告)号：US11831317B2
公开(公告)日：2023-11-28
申请号：US18064631
申请日：2022-12-12
摘要： A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.
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公开(公告)号：US11831314B1
公开(公告)日：2023-11-28
申请号：US17823655
申请日：2022-08-31
申请人： Apple Inc.
发明人： Simone del Cesta
CPC分类号： H03K3/011 , G05F3/245 , H03K3/023 , H03K3/0315 , H03L1/022
摘要： A ratiometric current source circuit having a reduced temperature dependence is disclosed. An embodiment of the current source circuit includes a first divider circuit configured to generate a reference voltage using a voltage level of a power supply node and a second divider circuit including a first resistor with a first temperature coefficient and a second resistor with a second temperature coefficient. The first resistor is configured to generate a first current using an input voltage and the voltage level of the power supply node and the second resistor is configured to generate a second current using the input voltage. The embodiment further includes a buffer circuit configured to generate the input voltage using the reference voltage and generate an output current using a difference between the first current and the second current.
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16.发明公开公开(公告)号：US20230370058A1
公开(公告)日：2023-11-16
申请号：US18317349
申请日：2023-05-15
发明人： Licinius-Pompiliu BENEA , Romain WACQUEZ , Florian PEBAY-PEYROULA , Vincent PUYAL , Mikael CARMONA , Michael PELISSIER
CPC分类号： H03K17/145 , H03K3/84 , H03K3/0315 , G06F7/588
摘要： A random number generator including at least one ring oscillator comprising at least one inverter formed by at least two FDSOI LVT transistors, one being of the NMOS type and the other one being of the PMOS type, and further including a circuit for applying voltages on rear gates of the transistors configured to bias the transistors in the FBB mode.
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公开(公告)号：US20230361777A1
公开(公告)日：2023-11-09
申请号：US18044410
申请日：2021-08-16
发明人： YOSHIAKI MORI , TETSUYA FUJIWARA
CPC分类号： H03L7/0992 , H03K5/134 , H03K3/0315
摘要： [Object]
Adjusting oscillator characteristics.
[Solving Means]
An oscillation device includes multiple delay elements that each sequentially delay an input signal, and return at least some of the delayed signals to a preceding stage to generate an oscillation signal, and a first control terminal that inputs, to the multiple delay elements, a direct current control signal for collectively controlling direct current voltage levels of the input signal to be input in plural number to the multiple delay elements.-
公开(公告)号：US11789064B1
公开(公告)日：2023-10-17
申请号：US17852181
申请日：2022-06-28
发明人： Huimei Zhou , Liqiao Qin , Miaomiao Wang , Effendi Leobandung
IPC分类号： G01R31/28 , G01R31/26 , G01R31/319 , H03K3/03 , H01L21/66
CPC分类号： G01R31/2824 , G01R31/2607 , G01R31/31924 , H01L22/34 , H03K3/0315
摘要： A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.
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公开(公告)号：US11775259B2
公开(公告)日：2023-10-03
申请号：US18046022
申请日：2022-10-12
CPC分类号： G06F7/582 , G06F7/588 , H03K3/0315 , H03K3/84
摘要： An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.
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公开(公告)号：US20230299752A1
公开(公告)日：2023-09-21
申请号：US17837055
申请日：2022-06-10
发明人： Chan CHEN , Anping QIU
CPC分类号： H03K3/011 , H03K3/0315 , H03K19/20 , G01R31/2849
摘要： Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.
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