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公开(公告)号：US20230396256A1
公开(公告)日：2023-12-07
申请号：US18169285
申请日：2023-02-15
发明人： Zhiqiang ZHANG
CPC分类号： H03L7/0814 , H03L7/087 , H03L7/091
摘要： A phase adjusting circuit, a delay locking circuit, and a memory are provided. The phase adjusting circuit includes a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence. The detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference is a preset value.
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公开(公告)号：US11750201B2
公开(公告)日：2023-09-05
申请号：US17347312
申请日：2021-06-14
申请人： SK hynix Inc.
发明人： Yun Tack Han , Kyeong Min Kim
CPC分类号： H03L7/0816 , H03K5/134 , H03L7/0895 , H03L7/087
摘要： A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
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公开(公告)号：US11728817B2
公开(公告)日：2023-08-15
申请号：US17567588
申请日：2022-01-03
发明人： Mrunmay Talegaonkar , Jorge Pernillo , Junyi Sun , Praveen Prabha , Chang-Feng Loi , Yu Liao , Jamal Riani , Belal Helal , Karthik S. Gopalakrishnan , Aaron Buchwald
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0807 , H03L7/099 , H04L7/0331
摘要： The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
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公开(公告)号：US11705911B2
公开(公告)日：2023-07-18
申请号：US17347312
申请日：2021-06-14
申请人： SK hynix Inc.
发明人： Yun Tack Han , Kyeong Min Kim
CPC分类号： H03L7/0816 , H03K5/134 , H03L7/0895 , H03L7/087
摘要： A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
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公开(公告)号：US11664811B2
公开(公告)日：2023-05-30
申请号：US16996109
申请日：2020-08-18
IPC分类号： G01C3/08 , H03L7/099 , H03L7/087 , G02B26/08 , G01S7/4863 , G01S7/4865 , G01S17/931
CPC分类号： H03L7/0992 , G01S7/4863 , G01S7/4865 , G01S17/931 , G02B26/0833 , H03L7/087
摘要： A system for driving a microelectromechanical system (MEMS) oscillating structure includes a phase error detector configured to generate a phase error signal based on measured event times and expected event times of the MEMS oscillating structure oscillating about a rotation axis; a disturbance event detector configured to detect a disturbance event based on the phase error signal and a disturbance threshold value; and a phase frequency detector (PFD) and correction circuit configured to, in response to the detected disturbance event, monitor for a plurality of measured crossing events of the MEMS oscillating structure oscillating about the rotation axis, generate a first compensation signal based on at least a first measured crossing event and a second measured crossing event to correct a frequency of the MEMS oscillating structure, and generate a second compensation signal based on a third measured crossing event to correct a phase of the MEMS oscillating structure.
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公开(公告)号：US11652445B2
公开(公告)日：2023-05-16
申请号：US17634602
申请日：2020-08-13
CPC分类号： H03B17/00 , H03L7/00 , H03L7/081 , H03L7/087 , H03L7/0816 , H04B10/50 , H03B2200/0044
摘要： An optoelectronic oscillator (OEO) including a drift compensation circuit is provided. The OEO includes a set of optical domain components communicatively coupled with a set of RF domain components. The RF domain components include a mode selection filter, a phase locked loop (PLL) and a drift compensation circuit communicatively coupled between the mode selection filter and the PLL. The mode selection filter provides a mode selection result to the drift compensation circuit. The drift compensation circuit phase modulates the mode selection result in a vector based coordinate system to maintain a drift compensated mode selection result within a locking bandwidth of the PLL, and to minimize phase shifting from accumulating phase drift. The PLL detects a phase difference between the drift compensated mode selection result and a reference signal, for use in maintaining the PLL in a phase lock with the reference signal, in particular over wide operational temperature ranges.
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公开(公告)号：US20230081578A1
公开(公告)日：2023-03-16
申请号：US17890817
申请日：2022-08-18
发明人： Jerzy A. Teterwak
摘要： A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
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公开(公告)号：US11588488B1
公开(公告)日：2023-02-21
申请号：US17546662
申请日：2021-12-09
申请人： Raytheon Company
发明人： Gary Ian Moore
摘要： A dual-loop phase-locking circuit combines a conventional phase-frequency-detector (PFD) and frequency-divider based first loop to lock an output signal frequency to a multiple of a reference signal frequency within a first loop bandwidth BW1 with a second loop to simultaneously lock the output signal phase to a second signal independently locked to the same multiple of the reference signal. The second loop integrates the phase error between the output signal and the second signal, and applies an offset at the PFD output in the first loop to reduce the first loop phase errors within a second loop bandwidth BW2 (
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公开(公告)号：US11558058B2
公开(公告)日：2023-01-17
申请号：US17514874
申请日：2021-10-29
申请人： SK hynix Inc.
发明人： Yun Tack Han , Kyeong Min Kim
摘要： A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
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公开(公告)号：US11509315B2
公开(公告)日：2022-11-22
申请号：US17462014
申请日：2021-08-31
申请人： MEDIATEK INC.
发明人： Po-Chun Huang , Yu-Li Hsueh
摘要： A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.
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