公开(公告)号：US20230185757A1

公开(公告)日：2023-06-15

申请号：US18063479

申请日：2022-12-08

申请人： Marvell Asia Pte Ltd

发明人： Michael Lewis Takefman ,  Arash Farhoodfar ,  Srinivas Swaminathan ,  Belal Helal

IPC分类号： G06F13/42 ,  H04B1/38 ,  H04B1/04

CPC分类号： G06F13/4291 ,  H04B1/38 ,  H04B1/0483

摘要： A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

公开(公告)号：US11218156B2

公开(公告)日：2022-01-04

申请号：US17013307

申请日：2020-09-04

申请人： Marvell Asia Pte Ltd.

发明人： Mrunmay Talegaonkar ,  Jorge Pernillo ,  Junyi Sun ,  Praveen Prabha ,  Chang-Feng Loi ,  Yu Liao ,  Jamal Riani ,  Belal Helal ,  Karthik Gopalakrishnan ,  Aaron Buchwald

IPC分类号： H03L7/197 ,  H04L7/033 ,  H03L7/087 ,  H03L7/08 ,  H03L7/099

摘要： The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

公开(公告)号：US11728817B2

公开(公告)日：2023-08-15

申请号：US17567588

申请日：2022-01-03

申请人： Marvell Asia Pte Ltd.

发明人： Mrunmay Talegaonkar ,  Jorge Pernillo ,  Junyi Sun ,  Praveen Prabha ,  Chang-Feng Loi ,  Yu Liao ,  Jamal Riani ,  Belal Helal ,  Karthik S. Gopalakrishnan ,  Aaron Buchwald

IPC分类号： H03L7/197 ,  H04L7/033 ,  H03L7/099 ,  H03L7/087 ,  H03L7/08

CPC分类号： H03L7/1976 ,  H03L7/087 ,  H03L7/0807 ,  H03L7/099 ,  H04L7/0331

摘要： The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.