专利检索 ap:("Marvell Asia Pte Ltd.") AND inv:"Aaron Buchwald" 第 1 页

$Clock and data recovery devices with fractional-N PLL$

1.

发明授权
Clock and data recovery devices with fractional-N PLL 有权

公开(公告)号：US11218156B2

公开(公告)日：2022-01-04

申请号：US17013307

申请日：2020-09-04

申请人： Marvell Asia Pte Ltd.

发明人： Mrunmay Talegaonkar , Jorge Pernillo , Junyi Sun , Praveen Prabha , Chang-Feng Loi , Yu Liao , Jamal Riani , Belal Helal , Karthik Gopalakrishnan , Aaron Buchwald

IPC分类号： H03L7/197 , H04L7/033 , H03L7/087 , H03L7/08 , H03L7/099

摘要： The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

$Clock and data recovery devices with fractional-N PLL$

2.

发明授权
Clock and data recovery devices with fractional-N PLL 有权

公开(公告)号：US11728817B2

公开(公告)日：2023-08-15

申请号：US17567588

申请日：2022-01-03

申请人： Marvell Asia Pte Ltd.

发明人： Mrunmay Talegaonkar , Jorge Pernillo , Junyi Sun , Praveen Prabha , Chang-Feng Loi , Yu Liao , Jamal Riani , Belal Helal , Karthik S. Gopalakrishnan , Aaron Buchwald

IPC分类号： H03L7/197 , H04L7/033 , H03L7/099 , H03L7/087 , H03L7/08

CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0807 , H03L7/099 , H04L7/0331

摘要： The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

3.

发明授权
Systems and methods for generating clock signals 有权

公开(公告)号：US11231741B1

公开(公告)日：2022-01-25

申请号：US16158153

申请日：2018-10-11

申请人： MARVELL ASIA PTE, LTD.

发明人： Aaron Buchwald

IPC分类号： G06F1/08 , H03L7/07

摘要： The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.