公开(公告)号：US20230185757A1

公开(公告)日：2023-06-15

申请号：US18063479

申请日：2022-12-08

Applicant: Marvell Asia Pte Ltd

Inventor： Michael Lewis Takefman ,  Arash Farhoodfar ,  Srinivas Swaminathan ,  Belal Helal

IPC: G06F13/42 ,  H04B1/38 ,  H04B1/04

CPC classification number: G06F13/4291 ,  H04B1/38 ,  H04B1/0483

Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

公开(公告)号：US12101186B2

公开(公告)日：2024-09-24

申请号：US18210823

申请日：2023-06-16

Applicant: Marvell Asia Pte Ltd

Inventor： Jamal Riani ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

IPC: H04L1/00 ,  H04L25/06

CPC classification number: H04L1/0071 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0045 ,  H04L1/0046 ,  H04L1/0055 ,  H04L1/0063 ,  H04L25/067

Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

公开(公告)号：US20230327806A1

公开(公告)日：2023-10-12

申请号：US18210823

申请日：2023-06-16

Applicant: Marvell Asia Pte Ltd

Inventor： Jamal RIANI ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

IPC: H04L1/00

CPC classification number: H04L1/0071 ,  H04L1/0055 ,  H04L1/0063 ,  H04L1/0042 ,  H04L1/0046

Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

公开(公告)号：US11683124B2

公开(公告)日：2023-06-20

申请号：US17677481

申请日：2022-02-22

Applicant: Marvell Asia Pte Ltd.

Inventor： Jamal Riani ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

IPC: H04L1/00

CPC classification number: H04L1/0071 ,  H04L1/0042 ,  H04L1/0046 ,  H04L1/0055 ,  H04L1/0063

Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

公开(公告)号：US12204486B2

公开(公告)日：2025-01-21

申请号：US18063479

申请日：2022-12-08

Applicant: Marvell Asia Pte Ltd

Inventor： Michael Lewis Takefman ,  Arash Farhoodfar ,  Srinivas Swaminathan ,  Belal Helal

IPC: G06F13/42 ,  H04B1/04 ,  H04B1/38

Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

公开(公告)号：US11265109B2

公开(公告)日：2022-03-01

申请号：US16824261

申请日：2020-03-19

Applicant: Marvell Asia Pte Ltd.

Inventor： Jamal Riani ,  Benjamin Smith ,  Volodymyr Shvydun ,  Srinivas Swaminathan ,  Arash Farhoodfar

IPC: H04L1/00

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.