TRANSMITTING CLOCK REFERENCE OVER REVERSE CHANNEL IN A BIDIRECTIONAL SERIAL LINK

    公开(公告)号:US20240348420A1

    公开(公告)日:2024-10-17

    申请号:US18647834

    申请日:2024-04-26

    发明人: Jerzy A. Teterwak

    摘要: A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

    Transmitting clock reference over reverse channel in a bidirectional serial link

    公开(公告)号:US12003612B2

    公开(公告)日:2024-06-04

    申请号:US17890817

    申请日:2022-08-18

    发明人: Jerzy A. Teterwak

    摘要: A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

    METHOD AND APPARATUS FOR SENSING CAPACITANCE VALUE AND CONVERTING IT INTO DIGITAL FORMAT
    3.
    发明申请
    METHOD AND APPARATUS FOR SENSING CAPACITANCE VALUE AND CONVERTING IT INTO DIGITAL FORMAT 审中-公开
    感知电容值的方法和装置,并将其转换为数字格式

    公开(公告)号:US20160025786A1

    公开(公告)日:2016-01-28

    申请号:US14875435

    申请日:2015-10-05

    IPC分类号: G01R27/26

    摘要: A capacitive sensing system are configured to sense a capacitance value and convert the sensed capacitance value to a digital format. The capacitive sensing system provides good selectivity and immunity to noise and interference, which can be further enhanced by enabling spread spectrum excitation. In some embodiments, the capacitive sensing system utilizes a sinusoidal excitation signal that results in low electromagnetic emissions, limited to narrow frequency band. In some embodiments, the capacitive sensing system is configured to operate in a spread spectrum mode, in which the majority of the excitation signal power is carried in the assigned bandwidth. The excitation frequency and the bandwidth of the spread spectrum excitation signal are programmable in a wide range, which allows for avoiding frequency conflicts in the operating environment.

    摘要翻译: 电容感测系统被配置为感测电容值并将所感测的电容值转换为数字格式。 电容感测系统为噪声和干扰提供了良好的选择性和抗扰度,可以通过启用扩频激励来进一步增强噪声和干扰。 在一些实施例中,电容感测系统利用导致低电磁辐射的正弦激励信号,限于窄频带。 在一些实施例中,电容感测系统被配置为以扩频模式工作,其中大部分激励信号功率以分配的带宽承载。 扩频激励信号的激励频率和带宽可在宽范围内编程,可以避免操作环境中的频率冲突。

    TRANSMITTING CLOCK REFERENCE OVER REVERSE CHANNEL IN A BIDIRECTIONAL SERIAL LINK

    公开(公告)号:US20230081578A1

    公开(公告)日:2023-03-16

    申请号:US17890817

    申请日:2022-08-18

    发明人: Jerzy A. Teterwak

    摘要: A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

    Method and apparatus for sensing capacitance value and converting it into digital format

    公开(公告)号:US09459298B2

    公开(公告)日:2016-10-04

    申请号:US14875435

    申请日:2015-10-05

    摘要: A capacitive sensing system are configured to sense a capacitance value and convert the sensed capacitance value to a digital format. The capacitive sensing system provides good selectivity and immunity to noise and interference, which can be further enhanced by enabling spread spectrum excitation. In some embodiments, the capacitive sensing system utilizes a sinusoidal excitation signal that results in low electromagnetic emissions, limited to narrow frequency band. In some embodiments, the capacitive sensing system is configured to operate in a spread spectrum mode, in which the majority of the excitation signal power is carried in the assigned bandwidth. The excitation frequency and the bandwidth of the spread spectrum excitation signal are programmable in a wide range, which allows for avoiding frequency conflicts in the operating environment.