公开(公告)号：US12057153B2

公开(公告)日：2024-08-06

申请号：US18074576

申请日：2022-12-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming Yuan Song

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1693 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.

公开(公告)号：US20240260479A1

公开(公告)日：2024-08-01

申请号：US18631813

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen CHIEN ,  Jung-Tang WU ,  Szu-Hua WU ,  Chin-Szu LEE ,  Meng-Yu WU

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20240260477A1

公开(公告)日：2024-08-01

申请号：US18364619

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Hyeonwoo SEO ,  YoungJun CHO

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/10

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10

Abstract: A method of manufacturing a magnetic memory device may include forming a bottom electrode layer on a substrate; forming a block structure on the bottom electrode layer; performing a first deposition process on the bottom electrode layer to form a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer on the bottom electrode layer; performing a second deposition process on the free magnetic layer to form a capping layer on the free magnetic layer; and performing an etching process after forming a hard mask on the capping layer to form magnetic tunnel junction patterns. The first deposition process may include irradiating a first beam toward the substrate. The second deposition process may include irradiating a second beam toward the substrate. The second beam may have a greater angle than the first beam with respect to a normal line perpendicular to an upper surface of the substrate.

公开(公告)号：US12051455B2

公开(公告)日：2024-07-30

申请号：US17845274

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jae Lee ,  Jihun Byun

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: A variable resistance memory device includes active regions apart from each other, common bit line contacts in the active regions, first active source contacts on first active regions near one edge of each of the common bit line contacts, second active source contacts on second active regions near another edge of each of the common bit line contacts, word lines between the first active source contacts and the common bit line contacts and between the common bit line contacts and the second active source contacts, bit lines on the common bit line contacts, variable resistance layers connected to the second active source contacts, the word lines, and the bit lines, spin-orbit torque (SOT) layers connected to the first active source contacts on the variable resistance layers, the word lines, and the bit lines, source line contacts on the SOT layers, and source lines connected to the source line contacts.

公开(公告)号：US20240251684A1

公开(公告)日：2024-07-25

申请号：US18626319

申请日：2024-04-03

Applicant: BEIJING INSTITUTE OF TECHNOLOGY ,  YANGTZE DELTA GRADUATE SCHOOL OF BIT (JIAXING)

Inventor： Shujun YE ,  Yeliang WANG

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: Provided are a magnetic random access memory device and a manufacturing method therefor. The device comprises magnetic thin film structure bodies, and an electrode arranged around side surfaces of the magnetic thin film structure body. The method is: preparing a bottom electrode, preparing a magnetic thin film structure body on the bottom electrode; preparing a non-magnetic thin film structure body on the magnetic thin film structure body, and preparing another magnetic thin film structure body on the non-magnetic thin film structure body; etching the two magnetic thin film structure bodies and the non-magnetic thin film structure body to form a MTJ device, preparing an insulating layer thin film on the outer surface of the device, and preparing a VCMA electrode on the periphery of the side face of the magnetic thin film structure body requiring voltage application; and preparing a wire connecting the VCMA electrode to outside.

公开(公告)号：US20240251568A1

公开(公告)日：2024-07-25

申请号：US18626670

申请日：2024-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  G11C11/1659

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US20240234000A1

公开(公告)日：2024-07-11

申请号：US18116836

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dmytro APALKOV ,  Roman CHEPULSKYY ,  Jaewoo JEONG ,  FNU IKHTIAR ,  Sungchul LEE

IPC: H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H01F10/3286 ,  G11C11/161 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: A perpendicular shape anisotropy magnetic tunnel junction structure includes a reference layer, a non-magnetic layer, and a free layer. The reference layer includes a first side and a second side opposite the first side. The non-magnetic spacer includes a first side and a second side. The first side of the non-magnetic spacer is on the second side of the first reference layer. The free layer includes a first side and a second side. The first side of the free layer is on the second side of the non-magnetic spacer. The free layer includes a first layer on the first side of the free layer, a second layer on the second side of the free layer and a coupling layer disposed between the first layer and the second layer. A ratio of a saturation magnetization of the second layer to a saturation magnetization of the first layer ranges from 0.2-0.8 inclusive.

公开(公告)号：US12035539B2

公开(公告)日：2024-07-09

申请号：US17480357

申请日：2021-09-21

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Baolei Wu ,  Xiaoguang Wang ,  Yulei Wu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10B61/10 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/22 ,  H10N50/80

Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.

公开(公告)号：US20240224812A1

公开(公告)日：2024-07-04

申请号：US18148392

申请日：2022-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Michael Rizzolo ,  Julien Frougier

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a magneto-resistive random access memory (MRAM) formed at a backside of a wafer. A self-aligning micro stud and silicide layer can directly electrically connect the MRAM to a source/drain (S/D) of a transistor in the MRAM region of the semiconductor device.

公开(公告)号：US20240215262A1

公开(公告)日：2024-06-27

申请号：US18601994

申请日：2024-03-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Min Lee ,  Ming-Yuan Song ,  Yen-Lin Huang ,  Shy-Jay Lin ,  Tung-Ying Lee ,  Xinyu BAO

IPC: H10B61/00 ,  G11C11/16 ,  G11C11/18 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10B61/22 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.