知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

1328 条记录 (耗时 0.018 秒)

    APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH
    13.
    发明申请
    APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH 有权

    公开(公告)号：US20170214403A1

    公开(公告)日：2017-07-27

    申请号：US15006646

    申请日：2016-01-26

    申请人： MICRON TECHNOLOGY, INC.

    发明人： TETSUYA ARAI

    IPC分类号： H03K19/00 ,  H03K19/003

    CPC分类号： H03K19/0013 ,  H03K19/0016 ,  H03K19/00384

    摘要： Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.

    INVERTER CIRCUITS
    14.
    发明申请
    INVERTER CIRCUITS 有权

    公开(公告)号：US20170170831A1

    公开(公告)日：2017-06-15

    申请号：US15086669

    申请日：2016-03-31

    申请人： SK hynix Inc.

    发明人： Jung Ho LIM ,  Jung Hwan JI

    IPC分类号： H03K19/003 ,  H03K5/06 ,  H03K19/20

    CPC分类号： H03K19/00384 ,  H03K5/06 ,  H03K19/20

    摘要： An inverter circuit includes a pull-up control circuit and a pull-up drive circuit. The pull-up control circuit generates a drive signal which is enabled during a first time period in response to an input signal and an output signal. The pull-up drive circuit drives the output signal to a power supply voltage in response to the input signal and the drive signal. The pull-up drive unit drives the output signal with a first drivability during the first time period and drives the output signal with a second drivability during a second time period.

    Integrated circuit device and repair method thereof
    16.
    发明授权
    Integrated circuit device and repair method thereof 有权
    集成电路装置及其修理方法

    公开(公告)号：US09508717B2

    公开(公告)日：2016-11-29

    申请号：US14797126

    申请日：2015-07-11

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： Zhenghao Gan

    IPC分类号： H03K19/003 ,  H01L27/092

    CPC分类号： H01L27/092 ,  H03K19/00315 ,  H03K19/00384

    摘要： The present disclosure provides integrated circuit (IC) devices and repair methods of the IC devices. An IC device includes a PMOS transistor including a substrate, a gate dielectric layer on the substrate, and a gate on the gate dielectric layer. The IC device also includes a repair circuit configured to apply a negative bias voltage to the substrate of the PMOS transistor, when the PMOS transistor is in an OFF state, to cause injections of electrons in the substrate into the gate dielectric layer to neutralize holes caused by negative bias temperature instability (NBTI) effect. The repair circuit is further configured to stop applying the negative bias voltage to the substrate of the PMOS transistor when the PMOS transistor is in an ON state. As such, the disclosed IC device repairs defect caused by NBTI effect in the PMOS transistor and prolongs the lifespan of the PMOS transistor.

    摘要翻译： 本公开提供了IC器件的集成电路（IC）器件和修复方法。 IC器件包括PMOS晶体管，其包括衬底，衬底上的栅极电介质层和栅极电介质层上的栅极。 IC器件还包括修复电路，该修复电路配置为当PMOS晶体管处于截止状态时向PMOS晶体管的衬底施加负偏压，以使衬底中的电子注入到栅介质层中以中和所引起的空穴 通过负偏压温度不稳定（NBTI）效应。 修复电路还被配置为当PMOS晶体管处于导通状态时，停止将负偏置电压施加到PMOS晶体管的衬底。 因此，所公开的IC器件修复由PMOS晶体管中的NBTI效应引起的缺陷并延长PMOS晶体管的寿命。

    Shift register circuit
    17.
    发明授权
    Shift register circuit 有权
    移位寄存器电路

    公开(公告)号：US09490809B2

    公开(公告)日：2016-11-08

    申请号：US14277918

    申请日：2014-05-15

    申请人： AU OPTRONICS CORP.

    发明人： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

    IPC分类号： G11C19/00 ,  H03K19/003 ,  G11C19/28

    CPC分类号： H03K19/00384 ,  G09G2310/0286 ,  G11C19/28

    摘要： A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.

    摘要翻译： 移位寄存器电路包括下拉电路，下拉控制电路，驱动单元，主下拉电路和栅极驱动器电路。 下拉控制电路电连接到下拉电路并且被配置为向下拉电路提供第n级下拉控制信号。 驱动单元电连接到下拉控制电路并且被配置为驱动下拉控制电路。 主下拉电路电连接到下拉电路。 栅极驱动器电路电连接到下拉电路并且被配置为根据第n级控制信号输出第n级栅极驱动信号。 驱动单元被配置为接收多个高频时钟信号，并相应地预先使能下拉控制电路，并且n是正整数。

    Input/output driver circuit, integrated circuit and method therefor
    18.
    发明授权
    Input/output driver circuit, integrated circuit and method therefor 有权
    输入/输出驱动电路，集成电路及其方法

    公开(公告)号：US09438236B2

    公开(公告)日：2016-09-06

    申请号：US14409310

    申请日：2012-07-06

    申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

    发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

    IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/017509 ,  H03K19/00384 ,  H03K19/018521

    摘要： An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

    摘要翻译： 描述了一个输入/输出（IO）驱动电路。 IO缓冲器驱动器电路包括：用于接收输入信号的至少一个输入和用于提供至少一个输出信号的至少一个输出; 以及多个开关，被布置成向所述至少一个输出端提供低电压值和高电压值之间的可变电压电平。 多个开关中的至少一个第一开关被布置成在第一时间段内启动电压变化到低电压值和高电压值之间的中间电压电平。 多个开关中的至少一个第二开关被布置成在第二时间段内将电压变化继续到低电压值或高电压值。

    Method and apparatus for a tunable driver circuit
    20.
    发明授权
    Method and apparatus for a tunable driver circuit 有权
    可调谐驱动电路的方法和装置

    公开(公告)号：US09407263B2

    公开(公告)日：2016-08-02

    申请号：US13665864

    申请日：2012-10-31

    申请人： FREESCALE SEMICONDUCTOR, INC.

    发明人： Alexander B. Hoefler ,  Hector Sanchez

    IPC分类号： H03K19/00 ,  H03K19/003

    CPC分类号： H03K19/0013 ,  H03K19/00384 ,  Y10T29/49155

    摘要： A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.

    摘要翻译： 具有可调节输出信号的驱动器电路包括被配置为将输入信号接收到第一输入端和与该逻辑电路相连的输出电路的逻辑电路，其中输出电路被配置为在输出电路的输出端产生 具有响应于输入信号的信号电平而变化的信号电平的输出信号。 驱动器电路还包括耦合到逻辑电路的第二输入端的反馈电路。 反馈电路包括耦合到输出端的第一和第二栅极端子和耦合到控制信号电源的第三栅极端子，其中反馈电路被配置为基于操作阈值来控制来自驱动器电路的输出信号的最大电平 由控制信号电源产生的控制信号设置的反馈电路。