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公开(公告)号：US09407263B2
公开(公告)日：2016-08-02
申请号：US13665864
申请日：2012-10-31
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/0013 , H03K19/00384 , Y10T29/49155
摘要： A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.
摘要翻译： 具有可调节输出信号的驱动器电路包括被配置为将输入信号接收到第一输入端和与该逻辑电路相连的输出电路的逻辑电路，其中输出电路被配置为在输出电路的输出端产生 具有响应于输入信号的信号电平而变化的信号电平的输出信号。 驱动器电路还包括耦合到逻辑电路的第二输入端的反馈电路。 反馈电路包括耦合到输出端的第一和第二栅极端子和耦合到控制信号电源的第三栅极端子，其中反馈电路被配置为基于操作阈值来控制来自驱动器电路的输出信号的最大电平 由控制信号电源产生的控制信号设置的反馈电路。
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公开(公告)号：US10417104B2
公开(公告)日：2019-09-17
申请号：US14861108
申请日：2015-09-22
IPC分类号： G06F11/27 , G01R31/3185
摘要： A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.
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公开(公告)号：US09264040B2
公开(公告)日：2016-02-16
申请号：US14134082
申请日：2013-12-19
CPC分类号： H03K19/0013
摘要： A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.
摘要翻译： 包含在包括PMOS晶体管和NMOS晶体管的集成电路上的CMOS单元。 PMOS和NMOS晶体管的当前端子串联耦合在较低电压的电源轨和参考轨道之间。 PMOS晶体管的阱连接耦合到具有大于低电压电源轨的电压电平的上电压电源轨。 CMOS电池具有低电压摆幅和低漏电流，以降低功耗。 可以包括第二PMOS和NMOS晶体管对并以类似的方式耦合到第一PMOS和NMOS对以形成非反相单元。 PMOS晶体管可以实现在导电地连接到上电源电压轨的N阱中，以避免隔离屏障。 该单元可以用在时钟树中以显着降低集成电路的功耗。
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公开(公告)号：US20150180452A1
公开(公告)日：2015-06-25
申请号：US14134082
申请日：2013-12-19
CPC分类号： H03K19/0013
摘要： A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.
摘要翻译： 包含在包括PMOS晶体管和NMOS晶体管的集成电路上的CMOS单元。 PMOS和NMOS晶体管的当前端子串联耦合在较低电压的电源轨和参考轨道之间。 PMOS晶体管的阱连接耦合到具有大于低电压电源轨的电压电平的上电压电源轨。 CMOS电池具有低电压摆幅和低漏电流，以降低功耗。 可以包括第二PMOS和NMOS晶体管对并以类似的方式耦合到第一PMOS和NMOS对以形成非反相单元。 PMOS晶体管可以实现在导电地连接到上电源电压轨的N阱中，以避免隔离屏障。 该单元可以用在时钟树中以显着降低集成电路的功耗。
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