公开(公告)号：US20130105942A1

公开(公告)日：2013-05-02

申请号：US13287331

申请日：2011-11-02

申请人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

发明人： Xiangdong Chen ,  Henry Chen ,  Agnes Woo ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L28/20 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/94

摘要： Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

摘要翻译： 公开了FinFET半导体器件的各种实施例。 可以形成一对共用的源极，漏极和/或沟道的匹配电容器。 因此，可以制造每个电容器的电容特性使得它们彼此相似。 还描述了采用FinFET技术制造的电阻器。 电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

公开(公告)号：US20130001687A1

公开(公告)日：2013-01-03

申请号：US13613864

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20120039106A1

公开(公告)日：2012-02-16

申请号：US13283418

申请日：2011-10-27

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/08

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US08836032B2

公开(公告)日：2014-09-16

申请号：US13277547

申请日：2011-10-20

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/12 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L2029/7857

摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.

摘要翻译： 根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。 鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。 翅片通道相对于第一和第二端子较低掺杂。 通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。 门可以在鳍通道的至少两侧。 在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。

公开(公告)号：US20130082330A1

公开(公告)日：2013-04-04

申请号：US13250563

申请日：2011-09-30

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/092 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

摘要翻译： 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。

公开(公告)号：US08363445B2

公开(公告)日：2013-01-29

申请号：US13283267

申请日：2011-10-27

申请人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

发明人： Frank Hui ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/115

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 可移位阈值电压晶体管具有漏极和栅极短路在一起。 编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。 在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。 编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

公开(公告)号：US20110108903A1

公开(公告)日：2011-05-12

申请号：US12590370

申请日：2009-11-06

申请人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

发明人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

摘要翻译： 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20110089490A1

公开(公告)日：2011-04-21

申请号：US12589357

申请日：2009-10-21

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20110037144A1

公开(公告)日：2011-02-17

申请号：US12583016

申请日：2009-08-13

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L28/90 ,  H01L29/94 ,  H01L29/945

摘要： According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

摘要翻译： 根据示例性实施例，在晶片中制造去耦复合电容器的方法包括覆盖在衬底上的电介质区域包括在电介质区域和衬底中形成贯通晶片通孔。 贯通晶片通孔包括覆盖贯通晶片通孔开口的侧壁和底部的贯通晶片通孔绝缘体，以及通过绝缘体覆盖贯通晶片的贯通晶片通孔导体。 该方法还包括使衬底变薄，形成衬底背面绝缘体，在衬底背面绝缘体中形成开口以通过导体暴露通过晶片，以及通过导体在透晶片上形成背面导体，使得衬底背侧导体 延伸到衬底背面绝缘体上，从而形成去耦复合电容器。 衬底形成第一去耦合复合电容器电极，并且通过晶片通孔导体和衬底背侧导体形成第二去耦复合电容器电极。

公开(公告)号：US20100284210A1

公开(公告)日：2010-11-11

申请号：US12387573

申请日：2009-05-05

申请人： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

发明人： Henry Kuo-Shun Chen ,  Xiangdong Chen ,  Wei Xia

IPC分类号： G11C17/00

CPC分类号： G11C17/16

摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.

摘要翻译： 根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的单元晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。 单元晶体管具有源极，栅极和与之短接在一起的主体。 响应于位线和字线上的编程电压，编程操作导致在单元晶体管的源极和漏极之间发生穿透。 单元晶体管的沟道长度基本上小于存取晶体管的沟道长度。 在一个实施例中，存取晶体管是NFET，而单元晶体管是PFET。 在另一个实施例中，存取晶体管是NFET，单元晶体管也是NFET。 各种实施例导致所需编程电压的降低。