公开(公告)号：US20230215801A1

公开(公告)日：2023-07-06

申请号：US17670520

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/7684 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US10600732B1

公开(公告)日：2020-03-24

申请号：US16122807

申请日：2018-09-05

Applicant: United Microelectronics Corp.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Yi-Hsiu Chen ,  Chih-Sheng Chang

IPC: H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate. An interconnection layer is formed on the substrate including a first inter-layer dielectric (ILD) layer over the substrate. A lower wiring structure is formed in the ILD layer. A hard mask layer is disposed on the first ILD layer. The hard mask layer has a first opening and a second opening being adjacent to expose the lower wiring structure. A second ILD layer is disposed on the hard mask layer. The second ILD layer has a via opening aligned to the first opening of the mask layer and a trench pattern connecting with the via opening. The second ILD layer has a protruding portion to fill the second opening of the mask layer. A metal line layer fills the via opening and the trench pattern in the second ILD layer and the first opening of the hard mask layer.

公开(公告)号：US20150041961A1

公开(公告)日：2015-02-12

申请号：US14521456

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Home-Been Cheng ,  Yu-Han Tsai ,  Ching-Li Yang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

Abstract translation: 公开了一种硅通孔结构。 贯通硅通孔包括：基板; 设置在所述基板上并具有多个第一开口的第一电介质层，所述多个第一开口的底部位于比所述基板的原始表面低的位置; 设置在所述第一电介质层和所述基板上的通孔，所述通孔与所述多个第一开口全部不重叠， 第二电介质层，其在填充所述多个第一开口的同时，设置在所述多个第一开口内和所述通孔的侧壁上; 以及设置在所述通孔内的导电材料层，所述导电材料层在所述通孔的侧壁上具有所述第二电介质层，从而形成通硅通孔。

公开(公告)号：US08916471B1

公开(公告)日：2014-12-23

申请号：US13975382

申请日：2013-08-26

Applicant: United Microelectronics Corp.

Inventor： Ching-Li Yang ,  Chien-Li Kuo ,  Chung-Sung Chiang ,  Yu-Han Tsai ,  Chun-Wei Kang

IPC: H01L21/44 ,  H01L29/40 ,  H01L21/768 ,  H01L23/552 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/3025

Abstract: A method for forming a through silicon via for signal and a shielding structure is provided. A substrate is provided and a region is defined on the substrate. A radio frequency (RF) circuit is formed in the region on the substrate. A through silicon trench (TST) and a through silicon via (TSV) are formed simultaneously, wherein the TST encompasses the region to serve as a shielding structure for the RF circuit. A metal interconnection system is formed on the substrate, wherein the metal interconnection system comprises a connection unit that electrically connects the TSV to the RF circuit to provide a voltage signal.

Abstract translation: 提供一种用于形成用于信号的通硅通孔和屏蔽结构的方法。 提供衬底并且在衬底上限定区域。 在基板上的区域中形成射频（RF）电路。 同时形成贯通硅沟槽（TST）和贯穿硅通孔（TSV），其中TST包围用作RF电路的屏蔽结构的区域。 在基板上形成金属互连系统，其中金属互连系统包括将TSV电连接到RF电路以提供电压信号的连接单元。