公开(公告)号：US10128251B2

公开(公告)日：2018-11-13

申请号：US15261845

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20180076205A1

公开(公告)日：2018-03-15

申请号：US15261845

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20160268125A1

公开(公告)日：2016-09-15

申请号：US14656733

申请日：2015-03-13

Applicant: United Microelectronics Corp.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/66 ,  H01L21/324

CPC classification number: H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract translation: 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。

公开(公告)号：US09443726B1

公开(公告)日：2016-09-13

申请号：US14656733

申请日：2015-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/321 ,  H01L21/66

CPC classification number: H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract translation: 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。

公开(公告)号：US20190035794A1

公开(公告)日：2019-01-31

申请号：US16151323

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20180277382A1

公开(公告)日：2018-09-27

申请号：US15904405

申请日：2018-02-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jen-Chieh Lin ,  Lee-Yuan Chen ,  Wen-Chin Lin ,  Chi-Lune Huang ,  Pi-Hung Chuang ,  Tai-Lin Chen ,  Sun-Hong Chen

IPC: H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/308

CPC classification number: H01L21/31055 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/3212 ,  H01L21/76802

Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.

公开(公告)号：US09384996B2

公开(公告)日：2016-07-05

申请号：US14272672

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

IPC: H01L21/3105 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层直到达到绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。

公开(公告)号：US20150325574A1

公开(公告)日：2015-11-12

申请号：US14272672

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

Abstract translation: 提供了一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层，直到到达绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。