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    Method of fabricating semiconductor device
    1.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09093465B2

    公开(公告)日：2015-07-28

    申请号：US14102515

    申请日：2013-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Ting Li ,  Po-Cheng Huang ,  Wu-Sian Sie ,  Chun-Hsiung Wang ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Rai-Min Huang

    IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/321 ,  H01L21/02

    CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/32055 ,  H01L21/3212 ,  H01L29/66795

    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

    Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少包括翅片结构的基板，并且形成材料层以覆盖翅片结构。 然后，在材料层上进行第一平面化处理以形成第一材料层，并且在第一材料层上形成氧化物层。 随后，完全除去氧化物层以露出第一材料层，并且在完全除去氧化物层之后，在第一材料层上原位形成第二材料层。

    SEMICONDUCTOR PROCESS
    2.
    发明申请
    SEMICONDUCTOR PROCESS 审中-公开
    半导体工艺

    公开(公告)号：US20150140819A1

    公开(公告)日：2015-05-21

    申请号：US14083456

    申请日：2013-11-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  I-Ming Tseng

    IPC: H01L21/3105 ,  H01L21/762

    CPC classification number: H01L21/31053 ,  H01L21/76224

    Abstract: A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided. A first oxide layer is formed to entirely cover the substrate. A prevention layer is formed on the first oxide layer. A first filling layer is formed on the prevention layer and fills the trenches until the first filling layer is higher than the substrate. A first polishing process is performed to polish the first filling layer until exposing the prevention layer. A second polishing process is performed to polish the first filling layer, the prevention layer and the first oxide layer until the substrate is exposed.

    Abstract translation: 半导体工艺包括以下步骤。 提供具有不同尺寸的沟槽的衬底。 形成第一氧化物层以完全覆盖衬底。 在第一氧化物层上形成防止层。 第一填充层形成在预防层上并填充沟槽直到第一填充层高于衬底。 执行第一抛光处理以抛光第一填充层直到暴露预防层。 进行第二抛光处理以抛光第一填充层，防止层和第一氧化物层，直到基板被暴露。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
    半导体结构及其工艺

    公开(公告)号：US20160336269A1

    公开(公告)日：2016-11-17

    申请号：US14709500

    申请日：2015-05-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

    IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

    Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

    Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    4.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权
    形成半导体结构的方法

    公开(公告)号：US20150147874A1

    公开(公告)日：2015-05-28

    申请号：US14088445

    申请日：2013-11-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L21/265

    CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

    Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

    Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

    Manufacturing method for a shallow trench isolation
    5.
    发明授权
    Manufacturing method for a shallow trench isolation 有权
    浅沟槽隔离的制造方法

    公开(公告)号：US09012300B2

    公开(公告)日：2015-04-21

    申请号：US13633104

    申请日：2012-10-01

    Applicant: United Microelectronics Corp.

    Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76232 ,  H01L21/76229

    Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

    Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上顺序地形成硬掩模层和图案化的光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

    Method of forming an isolation structure
    6.
    发明授权
    Method of forming an isolation structure 有权
    形成隔离结构的方法

    公开(公告)号：US08709901B1

    公开(公告)日：2014-04-29

    申请号：US13864277

    申请日：2013-04-17

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Lung Chang ,  Wu-Sian Sie ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chih-Chien Liu ,  Jui-Min Lee ,  Chih-Hsun Lin

    IPC: H01L21/336

    CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/32105

    Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

    Abstract translation: 本发明涉及一种形成隔离结构的方法，其中通过硬掩模在衬底中形成沟槽，并且进行沉积，回蚀刻，沉积，平坦化和回蚀以形成隔离 去除硬掩模后隔离结构的材料层。 可以形成硅层以在前一次沉积之前覆盖衬底的沟槽和原始表面，或者在前面的回蚀刻和稍后的沉积之前覆盖衬底的一部分沟槽和原始表面，以用作 停止层进行平面化处理。 存在于隔离材料层内的空隙可以通过由前面的回蚀部分蚀刻隔离材料层而被暴露或去除。 可以以较小的纵横比进行后续沉积以避免形成空隙。

    Manufacturing method of semiconductor device
    7.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US09466484B1

    公开(公告)日：2016-10-11

    申请号：US14859491

    申请日：2015-09-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Yu-Ting Li ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Wu-Sian Sie ,  I-Lun Hung ,  Chun-Tsen Lu ,  Shih-Ming Lin ,  Lan-Ping Chang

    IPC: H01L21/31 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11

    CPC classification number: H01L27/11 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/1116

    Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.

    Abstract translation: 提供一种半导体器件的制造方法。 该制造方法包括以下步骤。 在基板的第一区域和第二区域中形成多个翅片结构。 第一区域中的翅片结构的第一密度低于第二区域中的翅片结构的第二密度。 栅极电介质层形成在鳍结构上。 在第一区域和第二区域中的栅介质层和鳍结构上形成非晶硅层。 设置在第一区域中的非晶硅层的一部分被退火以通过激光形成晶体硅层。 设置在第一区域中的结晶硅层和设置在第二区域中的非晶硅层被抛光。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：US20150079780A1

    公开(公告)日：2015-03-19

    申请号：US14026634

    申请日：2013-09-13

    Applicant: United Microelectronics Corp.

    Inventor： Yl-Liang Liu ,  Wu-Sian Sie ,  Po-Cheng Huang ,  Chih-Hsien Chen ,  I-Lun Hung ,  Yen-Ming Chen ,  Yu-Ting Li ,  Chang-Hung Kung ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/78

    Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.

    Abstract translation: 公开了一种形成半导体器件的方法。 在基板上形成栅极结构。 栅极结构包括在虚拟栅极的侧壁处的伪栅极和间隔物。 在栅极结构外部的基板上形成电介质层。 形成金属硬掩模层以覆盖电介质层和间隔物的顶部并露出栅极结构的表面。 去除伪栅极以形成栅极沟槽。 在填充在栅极沟槽中的金属硬掩模层上形成低电阻率金属层。 除去栅极沟槽外的低电阻率金属层。 去除金属硬掩模层。

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