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公开(公告)号：US20210111120A1
公开(公告)日：2021-04-15
申请号：US17128194
申请日：2020-12-21
发明人： Guan-Yu Chen , An-Jhih Su , Der-Chyang Yeh , Li-Hsien Huang , Ming-Shih Yeh
IPC分类号： H01L23/522 , H01L23/00 , H01L23/42 , H01L23/31 , H01L21/56 , H01L21/822 , H01L25/10 , H01L25/00
摘要： A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.
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公开(公告)号：US20210020574A1
公开(公告)日：2021-01-21
申请号：US16671954
申请日：2019-11-01
发明人： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Tsung-Shu Lin
IPC分类号： H01L23/538 , H01L25/10 , H01L21/48 , H01L25/00
摘要： A structure includes a bridge die. The bridge die includes a semiconductor substrate; and an interconnect structure over the semiconductor substrate. The interconnect structure includes dielectric layers and conductive lines in the dielectric layers, an encapsulant encapsulating the bridge die therein, and a redistribution structure over the bridge die. The redistribution structure includes redistribution lines therein. A first package component and a second package component are bonded to the redistribution lines. The first package component and the second package component are electrically interconnected through the redistribution lines and the bridge die.
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公开(公告)号：US10811394B2
公开(公告)日：2020-10-20
申请号：US16458877
申请日：2019-07-01
发明人： Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC分类号： H01L25/065 , H01L21/56 , H01L21/48 , H01L21/78 , H01L23/31 , H01L23/498 , H01L25/00
摘要： A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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公开(公告)号：US20200286741A1
公开(公告)日：2020-09-10
申请号：US16881898
申请日：2020-05-22
发明人： Chen-Hua Yu , Der-Chyang Yeh
IPC分类号： H01L21/3105 , H01L25/00 , H01L23/00 , H01L23/31 , H01L21/56 , H01L25/065 , H01L25/18 , H01L21/683 , H01L23/48 , H01L23/498
摘要： A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip.
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公开(公告)号：US10741512B2
公开(公告)日：2020-08-11
申请号：US16687790
申请日：2019-11-19
发明人： Chi-Hsi Wu , Der-Chyang Yeh , Hsien-Wei Chen , Jie Chen
IPC分类号： H01L23/34 , H01L29/40 , H01L23/00 , H01L23/498 , H01L21/48 , H01L23/538 , H01L21/56 , H01L23/48 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/532 , H01L29/06
摘要： An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
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16.发明授权公开(公告)号：US10672741B2
公开(公告)日：2020-06-02
申请号：US15366654
申请日：2016-12-01
发明人： Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Hsien Huang , Yueh-Ting Lin , Wei-Yu Chen , An-Jhih Su
IPC分类号： H01L25/065 , H01L25/04 , H01L23/00 , H01L23/373 , H01L25/10 , H01L25/00 , H01L23/538 , H01L23/498
摘要： In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
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公开(公告)号：US10672647B2
公开(公告)日：2020-06-02
申请号：US16049499
申请日：2018-07-30
发明人： Chen-Hua Yu , Der-Chyang Yeh
IPC分类号： H01L21/768 , H01L23/31 , H01L23/00 , H01L23/538 , H01L21/56 , H01L25/10 , H05K3/42 , H05K3/46 , H01L23/498
摘要： Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
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公开(公告)号：US20200083156A1
公开(公告)日：2020-03-12
申请号：US16685645
申请日：2019-11-15
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC分类号： H01L23/498 , H01L23/58 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/31
摘要： A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
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公开(公告)号：US20200083145A1
公开(公告)日：2020-03-12
申请号：US16683672
申请日：2019-11-14
发明人： Jui-Pin Hung , Jing-Cheng Lin , Po-Hao Tsai , Yi-Jou Lin , Shuo-Mao Chen , Chiung-Han Yeh , Der-Chyang Yeh
IPC分类号： H01L23/48 , H01L23/31 , H01L21/56 , H01L21/48 , H01L25/00 , H01L25/18 , H01L23/00 , H01L21/82 , H01L21/768 , H01L25/10 , H01L23/538 , H01L23/498 , H01L23/28 , H01L25/065 , H01L23/528
摘要： An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
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公开(公告)号：US20200083061A1
公开(公告)日：2020-03-12
申请号：US16684741
申请日：2019-11-15
发明人： Hsien-Wei Chen , Chen-Hua Yu , Chi-Hsi Wu , Der-Chyang Yeh , An-Jhih Su , Wei-Yu Chen
摘要： A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
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