公开(公告)号：US20230065234A1

公开(公告)日：2023-03-02

申请号：US17459476

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pinyen LIN ,  Chin-Hsiang LIN ,  Huang-Lin CHAO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3115

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

公开(公告)号：US20210020786A1

公开(公告)日：2021-01-21

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer,

公开(公告)号：US20240405093A1

公开(公告)日：2024-12-05

申请号：US18328502

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Yang LEE ,  Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Pinyen LIN

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.

公开(公告)号：US20230207695A1

公开(公告)日：2023-06-29

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/78391 ,  H01L21/02068 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7851 ,  H01L29/40111 ,  H01L29/66795

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20230057278A1

公开(公告)日：2023-02-23

申请号：US17406879

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Chung-Liang CHENG ,  I-Ming CHANG ,  Yao-Sheng HUANG ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/3115

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

公开(公告)号：US20230040346A1

公开(公告)日：2023-02-09

申请号：US17701402

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Huang-Lin CHAO ,  Chung-Liang CHENG ,  Pinyen LIN ,  Chun-Chun LIN ,  Tzu-Li LEE ,  Yu-Chia LIANG ,  Duen-Huei HOU ,  Wen-Chung LIU ,  Chun-I WU

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

公开(公告)号：US20220077296A1

公开(公告)日：2022-03-10

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Ziwei FANG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US20210328065A1

公开(公告)日：2021-10-21

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20210083120A1

公开(公告)日：2021-03-18

申请号：US16572255

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

公开(公告)号：US20240088227A1

公开(公告)日：2024-03-14

申请号：US18516215

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.