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    GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
    11.
    发明申请
    GATE STRUCTURES FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200373206A1

    公开(公告)日：2020-11-26

    申请号：US16739676

    申请日：2020-01-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang CHENG ,  Ziwei FANG

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L29/49 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/28

    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

    SEMICONDUCTOR STRUCTURE HAVING METAL CONTACT FEATURES AND METHOD FOR FORMING THE SAME
    12.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING METAL CONTACT FEATURES AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20200294806A1

    公开(公告)日：2020-09-17

    申请号：US16353531

    申请日：2019-03-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang CHENG ,  Ziwei FANG

    IPC: H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

    Abstract: A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

    SEMICONDUCTOR DEVICE WITH TUNABLE WORK FUNCTION
    13.
    发明申请
    SEMICONDUCTOR DEVICE WITH TUNABLE WORK FUNCTION 有权
    具有可调功能的半导体器件

    公开(公告)号：US20160225871A1

    公开(公告)日：2016-08-04

    申请号：US14609138

    申请日：2015-01-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Liang CHENG ,  Wei-Jen CHEN ,  Yen-Yu CHEN ,  Wei ZHANG

    IPC: H01L29/51 ,  H01L29/423

    CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

    Abstract: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

    Abstract translation: 金属氧化物半导体结构包括衬底，栅极电介质多层，蚀刻停止层，功函数金属层，阻挡层和硅化物层。 衬底具有沟槽。 栅极电介质多层覆盖沟槽，其中栅极电介质多层包括氟浓度基本上在1at％至10at％范围内的高k覆盖层。 蚀刻停止层设置在栅极电介质多层上。 功函数金属层设置在蚀刻停止层上。 阻挡层设置在功函数金属层上。 硅化物层设置在阻挡层上。

    GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
    20.
    发明申请
    GATE STRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220320284A1

    公开(公告)日：2022-10-06

    申请号：US17837859

    申请日：2022-06-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu CHEN ,  Chung-Liang CHENG

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49

    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.

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