公开(公告)号：US11817489B2

公开(公告)日：2023-11-14

申请号：US17521344

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Chih-Yu Chang ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L29/516 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/66545

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

公开(公告)号：US11799030B2

公开(公告)日：2023-10-24

申请号：US17811212

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Han-Jong Chia ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/40111 ,  H01L29/516

Abstract: A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.

公开(公告)号：US11784242B2

公开(公告)日：2023-10-10

申请号：US17853104

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Po-Chi Wu ,  Che-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/66818 ,  H01L21/3065 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/165

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

公开(公告)号：US11764281B2

公开(公告)日：2023-09-19

申请号：US17874892

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ning Yao ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28123 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.

公开(公告)号：US11695073B2

公开(公告)日：2023-07-04

申请号：US17072367

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/24 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US11653500B2

公开(公告)日：2023-05-16

申请号：US17125435

申请日：2020-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L27/11597 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L23/535 ,  H01L27/1159 ,  H01L29/66

CPC classification number: H01L27/11597 ,  G11C11/2255 ,  H01L23/535 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/6684 ,  H01L29/66787 ,  H01L29/78391

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

公开(公告)号：US11631698B2

公开(公告)日：2023-04-18

申请号：US17070536

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11585 ,  H01L27/11578 ,  H01L27/11592 ,  H01L27/1159

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US11508753B2

公开(公告)日：2022-11-22

申请号：US16798719

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

IPC: H01L27/11 ,  H01L27/1159 ,  G11C11/22 ,  H01L27/12

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.

公开(公告)号：US11444202B2

公开(公告)日：2022-09-13

申请号：US16745340

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Chien-Ning Yao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.

公开(公告)号：US20220262809A1

公开(公告)日：2022-08-18

申请号：US17186852

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ming Lin ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Chi On Chui

IPC: H01L27/1159 ,  G11C8/14 ,  H01L27/11587 ,  H01L27/11597

Abstract: A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.