知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.023 seconds)

    MULTI-GATE SEMICONDUCTOR DEVICES
    12.
    发明申请
    MULTI-GATE SEMICONDUCTOR DEVICES 审中-公开
    多栅极半导体器件

    公开(公告)号：US20150162334A1

    公开(公告)日：2015-06-11

    申请号：US14624782

    申请日：2015-02-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

    IPC: H01L27/088 ,  H01L29/10 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

    Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

    Abstract translation: 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    13.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20230030571A1

    公开(公告)日：2023-02-02

    申请号：US17962327

    申请日：2022-10-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Ju LEE ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423

    Abstract: A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.

    MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
    16.
    发明申请
    MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 审中-公开
    多栅极半导体器件及其形成方法

    公开(公告)号：US20140103438A1

    公开(公告)日：2014-04-17

    申请号：US14108391

    申请日：2013-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ching WANG ,  Jon-Hsu HO ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Ken-Ichi GOTO ,  Zhiqiang WU

    IPC: H01L29/78

    CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

    Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

    Abstract translation: 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

    FIELD EFFECT TRANSISTOR WITH MERGED EPITAXY BACKSIDE CUT AND METHOD
    18.
    发明申请
    FIELD EFFECT TRANSISTOR WITH MERGED EPITAXY BACKSIDE CUT AND METHOD 有权

    公开(公告)号：US20220336613A1

    公开(公告)日：2022-10-20

    申请号：US17564125

    申请日：2021-12-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Ju LEE ,  Zhi-Chang LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

    Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

    AIR-REPLACED SPACER FOR SELF-ALIGNED CONTACT SCHEME
    19.
    发明申请
    AIR-REPLACED SPACER FOR SELF-ALIGNED CONTACT SCHEME 有权

    公开(公告)号：US20220181202A1

    公开(公告)日：2022-06-09

    申请号：US17682234

    申请日：2022-02-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Yu LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

    IPC: H01L21/768 ,  H01L21/02

    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    20.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210126135A1

    公开(公告)日：2021-04-29

    申请号：US16667615

    申请日：2019-10-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Ju LEE ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10 ,  H01L29/06

    Abstract: A semiconductor device includes a substrate, a plurality of nanowires, a gate structure, a source/drain epitaxy structure, and a semiconductor layer. The substrate has a protrusion portion. The nanowires extend in a first direction above the protrusion portion of the substrate, the nanowires being arranged in a second direction substantially perpendicular to the first direction. The gate structure wraps around each of the nanowires. The source/drain epitaxy structure is in contact with an end surface of each of the nanowires, in which a bottom surface of the source/drain epitaxy structure is lower than a top surface of the protrusion portion of the substrate. The semiconductor layer is in contact with the bottom surface of the epitaxy structure, in which the semiconductor layer is spaced from the protrusion portion of the substrate.

Patent Agency Ranking