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    BOTTOM ELECTRODE STRUCTURE FOR IMPROVED ELECTRIC FIELD UNIFORMITY
    13.
    发明申请
    BOTTOM ELECTRODE STRUCTURE FOR IMPROVED ELECTRIC FIELD UNIFORMITY 有权
    用于改善电场均匀性的底部电极结构

    公开(公告)号：US20170012198A1

    公开(公告)日：2017-01-12

    申请号：US15270251

    申请日：2016-09-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Shiou Huang ,  Cheng-Yuan Tsai ,  Yao-Wen Chang

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

    Abstract: A method for manufacturing an integrated circuit (IC) is provided. An etch is performed into an upper surface of an insulating layer to form an opening. A plurality of electrode layers is formed filling the opening. Forming the plurality of electrode layers comprises repeatedly forming an electrode layer conformally lining an unfilled region of the opening until the opening is filled. Forming the electrode layer comprises depositing the electrode layer and treating a surface of the electrode layer that faces an interior of the opening. A planarization is performed into the plurality of electrode layers to the upper surface of the insulating layer.

    Abstract translation: 提供一种用于制造集成电路（IC）的方法。 对绝缘层的上表面进行蚀刻以形成开口。 形成了填充开口的多个电极层。 形成多个电极层包括重复地形成保形地衬在开口的未填充区域的电极层，直到开口被填充。 形成电极层包括沉积电极层并处理电极层的面向开口内部的表面。 对绝缘层的上表面进行多个电极层的平坦化处理。

    Memory structure having top electrode with protrusion
    14.
    发明授权
    Memory structure having top electrode with protrusion 有权
    记忆结构，具有突出的顶部电极

    公开(公告)号：US09450183B2

    公开(公告)日：2016-09-20

    申请号：US14457170

    申请日：2014-08-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Shiou Huang ,  Yao-Wen Chang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai

    IPC: H01L47/00 ,  H01L45/00

    CPC classification number: H01L45/1273 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1666 ,  H01L45/1675

    Abstract: The present disclosure relates to an RRAM (resistive random access memory) cell having a top electrode with a geometry configured to improve the electric performance of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a lower insulating layer with a micro-trench located over a lower metal interconnect layer disposed within a lower inter-level dielectric (ILD) layer that overlies a semiconductor substrate. A bottom electrode is disposed over the micro-trench, and a dielectric data storage layer is located over the bottom electrode. A top electrode is disposed over the dielectric data storage layer. The top electrode has a protrusion that extends outward from a bottom surface of the top electrode at a position overlying the micro-trench. The protrusion generates a region having an enhanced electric field within the dielectric data storage layer, which improves performance of the RRAM cell.

    Abstract translation: 本公开涉及一种具有顶部电极的RRAM（电阻随机存取存储器）单元，其具有被配置为改善RRAM单元的电性能的几何形状以及相关联的形成方法。 在一些实施例中，RRAM单元具有下绝缘层，其中微沟槽位于布置在覆盖半​​导体衬底的下层间电介质（ILD）层内的下金属互连层上。 底部电极设置在微沟槽上方，并且电介质数据存储层位于底部电极之上。 顶部电极设置在电介质数据存储层上。 顶部电极具有从顶部电极的底表面向外延伸的突出部，该突出部位于覆盖微沟槽的位置。 突起产生在电介质数据存储层内具有增强电场的区域，这提高了RRAM单元的性能。

    BUFFER CAP LAYER TO IMPROVE MIM STRUCTURE PERFORMANCE
    15.
    发明申请
    BUFFER CAP LAYER TO IMPROVE MIM STRUCTURE PERFORMANCE 有权
    缓冲层提高MIM结构性能

    公开(公告)号：US20150349254A1

    公开(公告)日：2015-12-03

    申请号：US14289739

    申请日：2014-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Wen Chang ,  Jian-Shiou Huang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai

    IPC: H01L45/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L49/02

    CPC classification number: H01L21/31051 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

    Abstract: The present disclosure relates to method of forming a MIM (metal-insulator-metal) structure having a buffer cap layer that reduces stress induced by an overlying stress-inducing protective layer, and an associated apparatus. The method is performed by forming a lower conductive layer over a semiconductor substrate, forming a dielectric layer over the lower conductive layer, and forming an upper conductive layer over the dielectric layer. A buffer cap layer is formed over the upper conductive layer and a stress-inducing protective layer is formed onto the buffer cap layer. The buffer cap layer reduces a stress induced onto the upper conductive layer by the stress-inducing protective layer, thereby reducing leakage current between the lower and upper conductive layers.

    Abstract translation: 本公开内容涉及形成具有缓冲覆盖层的MIM（金属 - 绝缘体 - 金属）结构的方法，该缓冲覆盖层减少由上覆的应力诱导保护层引起的应力，以及相关联的装置。 该方法通过在半导体衬底上形成下导电层，在下导电层上形成电介质层，并在电介质层上形成上导电层。 在上导电层之上形成缓冲覆盖层，并且在缓冲覆盖层上形成应力诱导保护层。 缓冲覆盖层通过应力诱导保护层降低在上导电层上的应力，从而减少下导电层和上导电层之间的漏电流。

    Buffer cap layer to improve MIM structure performance
    19.
    发明授权
    Buffer cap layer to improve MIM structure performance 有权
    缓冲帽层，提高MIM结构性能

    公开(公告)号：US09425061B2

    公开(公告)日：2016-08-23

    申请号：US14289739

    申请日：2014-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Wen Chang ,  Jian-Shiou Huang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai

    IPC: H01L45/00 ,  H01L21/3105 ,  H01L49/02 ,  H01L21/02

    CPC classification number: H01L21/31051 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

    Abstract: The present disclosure relates to method of forming a MIM (metal-insulator-metal) structure having a buffer cap layer that reduces stress induced by an overlying stress-inducing protective layer, and an associated apparatus. The method is performed by forming a lower conductive layer over a semiconductor substrate, forming a dielectric layer over the lower conductive layer, and forming an upper conductive layer over the dielectric layer. A buffer cap layer is formed over the upper conductive layer and a stress-inducing protective layer is formed onto the buffer cap layer. The buffer cap layer reduces a stress induced onto the upper conductive layer by the stress-inducing protective layer, thereby reducing leakage current between the lower and upper conductive layers.

    Abstract translation: 本公开内容涉及形成具有缓冲覆盖层的MIM（金属 - 绝缘体 - 金属）结构的方法，该缓冲覆盖层减少由上覆的应力诱导保护层引起的应力，以及相关联的装置。 该方法通过在半导体衬底上形成下导电层，在下导电层上形成电介质层，并在电介质层上形成上导电层。 在上导电层之上形成缓冲覆盖层，并且在缓冲覆盖层上形成应力诱导保护层。 缓冲覆盖层通过应力诱导保护层降低在上导电层上的应力，从而减少下导电层和上导电层之间的漏电流。

    MEMORY STRUCTURE HAVING TOP ELECTRODE WITH PROTRUSION
    20.
    发明申请
    MEMORY STRUCTURE HAVING TOP ELECTRODE WITH PROTRUSION 有权
    具有顶端电极的记忆结构

    公开(公告)号：US20160049583A1

    公开(公告)日：2016-02-18

    申请号：US14457170

    申请日：2014-08-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jian-Shiou Huang ,  Yao-Wen Chang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai

    IPC: H01L45/00

    CPC classification number: H01L45/1273 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1666 ,  H01L45/1675

    Abstract: The present disclosure relates to an RRAM (resistive random access memory) cell having a top electrode with a geometry configured to improve the electric performance of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a lower insulating layer with a micro-trench located over a lower metal interconnect layer disposed within a lower inter-level dielectric (ILD) layer that overlies a semiconductor substrate. A bottom electrode is disposed over the micro-trench, and a dielectric data storage layer is located over the bottom electrode. A top electrode is disposed over the dielectric data storage layer. The top electrode has a protrusion that extends outward from a bottom surface of the top electrode at a position overlying the micro-trench. The protrusion generates a region having an enhanced electric field within the dielectric data storage layer, which improves performance of the RRAM cell.

    Abstract translation: 本公开涉及一种具有顶部电极的RRAM（电阻随机存取存储器）单元，其具有被配置为改善RRAM单元的电性能的几何形状以及相关联的形成方法。 在一些实施例中，RRAM单元具有下绝缘层，其中微沟槽位于布置在覆盖半​​导体衬底的下层间电介质（ILD）层内的下金属互连层上。 底部电极设置在微沟槽上方，并且电介质数据存储层位于底部电极之上。 顶部电极设置在电介质数据存储层上。 顶部电极具有从顶部电极的底表面向外延伸的突出部，该突出部位于覆盖微沟槽的位置。 突起产生在电介质数据存储层内具有增强电场的区域，这提高了RRAM单元的性能。

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