公开(公告)号：US11581416B1

公开(公告)日：2023-02-14

申请号：US17406879

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/40

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

公开(公告)号：US12148843B2

公开(公告)日：2024-11-19

申请号：US18316550

申请日：2023-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Chang ,  Hsiang-Pi Chang ,  Zi-Wei Fang

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a silicon germanium channel, a germanium-free interfacial layer, a high-k dielectric layer, and a metal gate electrode. The silicon germanium channel is over a substrate. The germanium-free interfacial layer is over the silicon germanium channel. The germanium-free interfacial layer is nitridated. The high-k dielectric layer is over the germanium-free interfacial layer. The metal gate electrode is over the high-k dielectric layer.

公开(公告)号：US11710779B2

公开(公告)日：2023-07-25

申请号：US17301482

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Yu-Wei Lu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823807 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/785

Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.

公开(公告)号：US11031508B2

公开(公告)日：2021-06-08

申请号：US16853602

申请日：2020-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Chang ,  Hsiang-Pi Chang ,  Zi-Wei Fang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/10 ,  H01L29/08 ,  H01L21/324 ,  H01L21/28 ,  H01L21/265

Abstract: A semiconductor device includes a source region, a drain region, a SiGe channel region, an interfacial layer, a high-k dielectric layer and a gate electrode. The source region and the drain region are over a substrate. The SiGe channel region is laterally between the source region and the drain region. The interfacial layer forms a nitrogen-containing interface with the SiGe channel region. The high-k dielectric layer is over the interfacial layer. The gate electrode is over the high-k dielectric layer.

公开(公告)号：US09960085B2

公开(公告)日：2018-05-01

申请号：US15001364

申请日：2016-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Hung-Chang Sun ,  Lung-Kun Chu

IPC: H01L21/338 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/092 ,  H01L29/4966

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.