公开(公告)号：US20230369396A1

公开(公告)日：2023-11-16

申请号：US18165853

申请日：2023-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chien CHENG ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Guan-Lin CHEN ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823481

Abstract: A device includes a stack of first semiconductor nanostructures over a substrate and a stack of second semiconductor nanostructures over the substrate. The device includes an isolation structure between the first and second semiconductor nanostructures. The isolation structure includes a core dielectric layer extending from below a top surface of the substrate to a level higher than all of the first and second semiconductor nanostructures. The isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the semiconductor nanostructures. The spaces between the core dielectric layer and each of the semiconductor nanostructures can be filled with gate dielectric material or with remnants of the shell dielectric layer.

公开(公告)号：US20220352150A1

公开(公告)日：2022-11-03

申请号：US17484956

申请日：2021-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Jung-Chien CHENG ,  Shi-Ning JU ,  Guan-Lin CHEN ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

公开(公告)号：US20220037496A1

公开(公告)日：2022-02-03

申请号：US17302395

申请日：2021-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin CHEN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

公开(公告)号：US20240395857A1

公开(公告)日：2024-11-28

申请号：US18789179

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Rong LIN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Guan-Lin CHEN ,  Jung-Chien CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate and a transistor. The transistor includes a first channel region overlying the substrate and a source/drain region in contact with the first channel region. The source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region.

公开(公告)号：US20230387236A1

公开(公告)日：2023-11-30

申请号：US18446151

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin CHEN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/78696 ,  H01L29/66545

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

公开(公告)号：US20210135008A1

公开(公告)日：2021-05-06

申请号：US16834264

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Guan-Lin CHEN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the stressor structure.