公开(公告)号：US20230134161A1

公开(公告)日：2023-05-04

申请号：US17704882

申请日：2022-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Chien CHENG ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Guan-Lin CHEN ,  Bo-Rong LIN ,  Chih-Hao WANG

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/66

Abstract: An integrated circuit includes a transistor having a plurality of semiconductor nanostructures arranged in a stack and corresponding to channel regions of the transistor. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide that extends downward along a side of the source/drain region.

公开(公告)号：US20240379878A1

公开(公告)日：2024-11-14

申请号：US18784490

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20230402536A1

公开(公告)日：2023-12-14

申请号：US18163857

申请日：2023-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Guan-Lin CHEN ,  Shi Ning JU ,  Jung-Chien CHENG ,  Chih-Hao WANG

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439

Abstract: A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.

公开(公告)号：US20230387109A1

公开(公告)日：2023-11-30

申请号：US18447881

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Jung-Chien CHENG ,  Shi-Ning JU ,  Guan-Lin CHEN ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/66477 ,  H01L29/4232 ,  H01L21/76224 ,  H01L29/0649

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

公开(公告)号：US20220359652A1

公开(公告)日：2022-11-10

申请号：US17562794

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Rong LIN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Guan-Lin CHEN ,  Jung-Chien CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate and a transistor. The transistor includes a first channel region overlying the substrate and a source/drain region in contact with the first channel region. The source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region.

公开(公告)号：US20210135011A1

公开(公告)日：2021-05-06

申请号：US16834440

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Guan-Lin CHEN ,  Chih-Hao WANG

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/3105

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

公开(公告)号：US20250151326A1

公开(公告)日：2025-05-08

申请号：US18646578

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin CHEN ,  Chih-Hao WANG ,  Pei-Yu WANG ,  Hsien-Chih HUANG ,  Chia-Hao YU

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

公开(公告)号：US20230014998A1

公开(公告)日：2023-01-19

申请号：US17379936

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20210159311A1

公开(公告)日：2021-05-27

申请号：US16697647

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting LAN ,  Guan-Lin CHEN ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap.

公开(公告)号：US20250006548A1

公开(公告)日：2025-01-02

申请号：US18499908

申请日：2023-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Chih HUANG ,  Guan-Lin CHEN ,  Chia-Hao CHANG ,  Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.