公开(公告)号：US20160161838A1

公开(公告)日：2016-06-09

申请号：US15010856

申请日：2016-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao YU ,  Ming-Yun CHEN

IPC: G03F1/24 ,  G03F1/72 ,  G03F1/80 ,  G03F1/76

CPC classification number: G03F1/24 ,  G03F1/22 ,  G03F1/72 ,  G03F1/76 ,  G03F1/80

Abstract: Any defects in the reflective multilayer coating or absorber layer of an EUV mask are problematic in transferring a pattern of the EUV mask to a wafer since they produce errors in integrated circuit patterns on the wafer. In this regard, a method of manufacturing an EUV mask is provided according to various embodiments of the present disclosure. To repair the defect, a columnar reflector, which acts as a Bragg reflector, is deposited according to various embodiments so as to locally compensate and repair the defect. According to the embodiments of the present disclosure, the reflective loss due to the defect can be compensated and recover the phase different due to the defect from, so as to form a desirable wafer printed image.

Abstract translation: EUV掩模的反射多层涂层或吸收层中的任何缺陷在将EUV掩模的图案转印到晶片上是有问题的，因为它们在晶片上产生集成电路图案的错误。 在这方面，根据本公开的各种实施例提供了制造EUV掩模的方法。 为了修复缺陷，根据各种实施例沉积充当布拉格反射器的柱状反射体，以局部补偿和修复缺陷。 根据本公开的实施例，可以补偿由于缺陷引起的反射损耗，并且恢复由于缺陷而导致的相位不同，从而形成期望的晶片印刷图像。

公开(公告)号：US20250151326A1

公开(公告)日：2025-05-08

申请号：US18646578

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin CHEN ,  Chih-Hao WANG ,  Pei-Yu WANG ,  Hsien-Chih HUANG ,  Chia-Hao YU

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

公开(公告)号：US20250072065A1

公开(公告)日：2025-02-27

申请号：US18405526

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung CHANG ,  Shih-Cheng CHEN ,  Chia-Hao YU ,  Chia-Cheng TSAI ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A device includes: a substrate; a stack of semiconductor channels on the substrate; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; and a hybrid structure between the source/drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source/drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.