公开(公告)号：US20200350209A1

公开(公告)日：2020-11-05

申请号：US16933676

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Cheng-Lin Huang ,  Wen-Ming Chen

IPC: H01L21/82 ,  H01L23/00 ,  H01L21/268 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.

公开(公告)号：US20200343265A1

公开(公告)日：2020-10-29

申请号：US16394207

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

公开(公告)号：US11849588B2

公开(公告)日：2023-12-19

申请号：US17712543

申请日：2022-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Tzu-Yu Chen ,  Sheng-Hung Shih

IPC: G11C11/22 ,  H10B51/30 ,  H01L49/02 ,  H10B51/10 ,  H10B53/00 ,  H10B53/30

CPC classification number: H10B51/30 ,  G11C11/223 ,  H01L28/57 ,  H01L28/60 ,  H10B51/10 ,  H10B53/00 ,  H10B53/30

Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.

公开(公告)号：US11723213B2

公开(公告)日：2023-08-08

申请号：US17376531

申请日：2021-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Fu-Chen Chang

IPC: H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/60

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

公开(公告)号：US11296116B2

公开(公告)日：2022-04-05

申请号：US16727673

申请日：2019-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Tzu-Yu Chen ,  Sheng-Hung Shih

IPC: H01L27/11 ,  H01L27/1159 ,  H01L27/11587 ,  G11C11/22 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/11502

Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.

公开(公告)号：US11227872B2

公开(公告)日：2022-01-18

申请号：US16394207

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

公开(公告)号：US11189788B2

公开(公告)日：2021-11-30

申请号：US16395620

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

公开(公告)号：US11183503B2

公开(公告)日：2021-11-23

申请号：US16663952

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22 ,  H01L27/11504

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

公开(公告)号：US10535554B2

公开(公告)日：2020-01-14

申请号：US15725558

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Tang ,  Fu-Chen Chang ,  Cheng-Lin Huang ,  Chun-Yen Lo ,  Wen-Ming Chen ,  Kuo-Chio Liu

IPC: H01L23/495 ,  H01L23/522 ,  H01L21/304 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L23/498 ,  H01L25/10 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.