-
公开(公告)号：US09773731B2
公开(公告)日：2017-09-26
申请号：US15009500
申请日：2016-01-28
发明人： Chia-Hsin Hu , Yu-Chiun Lin , Yi-Hsuan Chung , Chung-Peng Hsieh , Chung-Chieh Yang , Po-Nien Chen
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L23/5228 , H01L27/11582 , H01L28/00 , H01L28/24
摘要： A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
-
公开(公告)号：US12073167B2
公开(公告)日：2024-08-27
申请号：US18163916
申请日：2023-02-03
发明人： Chung-Ting Lu , Chih-Chiang Chang , Chung-Peng Hsieh , Chung-Chieh Yang , Yung-Chow Peng , Yung-Shun Chen , Tai-Yi Chen , Nai Chen Cheng
IPC分类号： G06F30/392 , G06F30/36 , G06F30/367 , G06F30/394
CPC分类号： G06F30/392 , G06F30/36 , G06F30/367 , G06F30/394
摘要： An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.
-
公开(公告)号：US11567105B2
公开(公告)日：2023-01-31
申请号：US17326147
申请日：2021-05-20
IPC分类号： G01R19/00 , G01R13/00 , G01R13/02 , G01R31/28 , G01R31/317
摘要： A device includes a control circuit, a scope circuit, and a time-to-current converter. The control circuit is configured to receive a voltage signal from a voltage-controlled oscillator, delay the voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit is configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter is configured generate a second current signal according to the first control signal, the voltage signal, a first switch signal, and a test control signal.
-
公开(公告)号：US10886190B2
公开(公告)日：2021-01-05
申请号：US16681687
申请日：2019-11-12
发明人： Chung-Chieh Yang , Yung-Chow Peng , Chung-Peng Hsieh , Sa-Lly Liu
IPC分类号： H01L29/00 , H01L23/34 , H01L23/64 , H01L23/552 , H01L23/522 , H01L49/02
摘要： A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.
-
公开(公告)号：US20190067150A1
公开(公告)日：2019-02-28
申请号：US15883462
申请日：2018-01-30
发明人： Chung-Chieh Yang , Yung-Chow Peng , Chung-Peng Hsieh , Sa-Lly Liu
IPC分类号： H01L23/34 , H01L23/552 , H01L23/64
摘要： A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.
-
公开(公告)号：US10163809B2
公开(公告)日：2018-12-25
申请号：US14944907
申请日：2015-11-18
发明人： Jaw-Juinn Horng , Chung-Peng Hsieh
IPC分类号： H01L23/552 , H01L23/48 , H01L23/58 , H01L25/065 , H01L23/528 , H01L23/538
摘要： In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.
-
公开(公告)号：US09219038B2
公开(公告)日：2015-12-22
申请号：US13795035
申请日：2013-03-12
发明人： Jaw-Juinn Horng , Chung-Peng Hsieh
IPC分类号： H01L29/40 , H01L23/552 , H01L23/48 , H01L23/58 , H01L25/065
CPC分类号： H01L23/552 , H01L23/481 , H01L23/528 , H01L23/5384 , H01L23/5386 , H01L23/585 , H01L25/0657 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： 3D integrated circuit devices include first and second semiconductor bodies. The first semiconductor body has an active area, a through-silicon-via outside the active area, and two or more disjoint guard rings. The first guard ring encircles the via. The second guard ring encircles the active area, but not the via. The guard rings can reduce the noise coupling coefficient between the via and the active area to −60 dB or less at 3 GHz and 20 μm spacing.
摘要翻译： 3D集成电路器件包括第一和第二半导体本体。 第一半导体本体具有有源区域，有源区域外的穿硅通孔以及两个或更多个不相交的保护环。 第一个护环环绕通道。 第二个保护环环绕活动区域，但不包括通道。 保护环可以将通孔和有源区域之间的噪声耦合系数降低到3 GHz和20μm间距的-60 dB或更小。
-
公开(公告)号：US11035886B2
公开(公告)日：2021-06-15
申请号：US16212090
申请日：2018-12-06
IPC分类号： G01R19/00 , G01R13/00 , G01R13/02 , G01R31/28 , G01R31/317
摘要： A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.
-
公开(公告)号：US10770404B2
公开(公告)日：2020-09-08
申请号：US16220236
申请日：2018-12-14
发明人： Jaw-Juinn Horng , Chung-Peng Hsieh
IPC分类号： H01L23/552 , H01L23/48 , H01L23/58 , H01L25/065 , H01L23/528 , H01L23/538
摘要： In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.
-
公开(公告)号：US20190122997A1
公开(公告)日：2019-04-25
申请号：US16220236
申请日：2018-12-14
发明人： Jaw-Juinn Horng , Chung-Peng Hsieh
IPC分类号： H01L23/552 , H01L23/58 , H01L23/538 , H01L25/065 , H01L23/528 , H01L23/48
CPC分类号： H01L23/552 , H01L23/481 , H01L23/528 , H01L23/5384 , H01L23/5386 , H01L23/585 , H01L25/0657 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.022 秒)
