公开(公告)号：US11906898B2

公开(公告)日：2024-02-20

申请号：US16989744

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Tien ,  Cheng-Hsuen Chiang ,  Chih-Ming Chen ,  Cheng-Ming Lin ,  Yen-Wei Huang ,  Hao-Ming Chang ,  Kuo-Chin Lin ,  Kuan-Shien Lee

IPC: G03F1/32 ,  G03F1/38 ,  H01L21/308 ,  G03F1/80

CPC classification number: G03F1/32 ,  G03F1/38 ,  G03F1/80 ,  H01L21/3083

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

公开(公告)号：US20230367197A1

公开(公告)日：2023-11-16

申请号：US18359954

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ta Lu ,  Chih-Chiang Tu ,  Cheng-Ming Lin ,  Ching-Yueh Chen ,  Wei-Chung Hu ,  Ting-Chang Hsu ,  Yu-Tung Chen

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/36 ,  G03F1/64 ,  G03F1/38 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/36 ,  G03F1/38 ,  G03F1/54 ,  G03F1/64 ,  G03F7/2004

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

公开(公告)号：US20230110241A1

公开(公告)日：2023-04-13

申请号：US18065442

申请日：2022-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.

公开(公告)号：US11594633B2

公开(公告)日：2023-02-28

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20220285221A1

公开(公告)日：2022-09-08

申请号：US17550670

申请日：2021-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Wei-Yen Woon ,  Cheng-Ming Lin ,  Han-Yu Lin ,  Szu-Hua Chen ,  Jhih-Rong Huang ,  Tzer-Min Shen

IPC: H01L21/8234 ,  H01L21/48 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

公开(公告)号：US11048163B2

公开(公告)日：2021-06-29

申请号：US15832752

申请日：2017-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Cheng Tang ,  Cheng-Ming Lin ,  Sheng-Chang Hsu ,  Hao-Ming Chang ,  Waylen Chang

IPC: G03F1/84 ,  G03F1/42 ,  G03F7/20 ,  G01N21/95 ,  G01B11/02 ,  G01N21/88

Abstract: In accordance with some embodiments of the present disclosure, an inspection method of a photomask includes performing a first inspection process, unloading the photomask from the inspection system, and performing a second inspection process. In the first inspection process, a common Z calibration map of an objective lens of an optical module with respect to the photomask is generated and stored, and a first image of the photomask is captured by using an image sensor while focusing the objective lens of the optical module based on the common Z calibration map. The photomask is unloaded from the inspection system. In the second inspection process, the photomask is loaded on the inspection system and a second image of the photomask is captured by using an image sensor while focusing an objective lens of an optical module based on the common Z calibration map generated in the first inspection process.

公开(公告)号：US10665685B2

公开(公告)日：2020-05-26

申请号：US16059900

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.

公开(公告)号：US20200127111A1

公开(公告)日：2020-04-23

申请号：US16218151

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Kai Tak Lam ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.

公开(公告)号：US10508953B2

公开(公告)日：2019-12-17

申请号：US15490075

申请日：2017-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-An Yang ,  Hao-Ming Chang ,  Shao-Chi Wei ,  Kuo-Chin Lin ,  Sheng-Chang Hsu ,  Li-Chih Lu ,  Cheng-Ming Lin

IPC: G01J5/00 ,  H01L21/67 ,  G01J5/10

Abstract: A method for processing a substrate is provided. The method includes supplying a first flow of a chemical solution into a processing chamber, configured to process the substrate, via a first dispensing nozzle. The method further includes producing a first thermal image of the first flow of the chemical solution. The method also includes performing an image analysis on the first thermal image. In addition, the method includes moving the substrate into the processing chamber when the result of the analysis of the first thermal image is within the allowable deviation from the baseline.

公开(公告)号：US12136570B2

公开(公告)日：2024-11-05

申请号：US17550670

申请日：2021-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Wei-Yen Woon ,  Cheng-Ming Lin ,  Han-Yu Lin ,  Szu-Hua Chen ,  Jhih-Rong Huang ,  Tzer-Min Shen

IPC: H01L21/8234 ,  H01L21/48 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.