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    WIDE BANDGAP POWER DEVICES WITH LOW POWER LOOP INDUCTANCE
    11.
    发明申请
    WIDE BANDGAP POWER DEVICES WITH LOW POWER LOOP INDUCTANCE 有权

    公开(公告)号：US20250112126A1

    公开(公告)日：2025-04-03

    申请号：US18478715

    申请日：2023-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jie CHEN ,  Sylvester ANKAMAH-KUSI ,  Rajen Manicon MURUGAN ,  Yong XIE ,  Danny Lee BRIJA

    IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778

    Abstract: In examples, a power device comprises a first wide bandgap semiconductor die including a high-side transistor; a second wide bandgap semiconductor die including a low-side transistor; and a conductive device coupled to the first and second wide bandgap semiconductor dies. The conductive device comprises a first layer including a first metal member having fingers at first and second ends of the first metal member, a second metal member having fingers interleaved with fingers of the first metal member at the first end, and a third metal member having fingers interleaved with fingers of the first metal member at the second end. The conductive device also comprises multiple layers in vertical alignment with the first layer, the first, second, and third metal members extending through the multiple layers. The conductive device also comprises a dielectric material covering the first layer and the multiple layers. The power device comprises a connection layer coupling the conductive device to each of the first and second wide bandgap semiconductor dies, with the connection layer including the first, second, and third metal members, and with the first metal member having connection layer fingers at the first and second ends of the first metal member. The second metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the first end, and the third metal member has connection layer fingers interleaved with connection layer fingers of the first metal member at the second end.

    SEMICONDUCTOR PACKAGES WITH DIRECTIONAL ANTENNAS
    14.
    发明公开
    SEMICONDUCTOR PACKAGES WITH DIRECTIONAL ANTENNAS 审中-公开

    公开(公告)号：US20240113050A1

    公开(公告)日：2024-04-04

    申请号：US17956798

    申请日：2022-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Juan HERBSOMMER ,  Yiqi TANG ,  Rajen Manicon MURUGAN

    IPC: H01L23/66 ,  H01Q1/22 ,  H01Q13/02

    CPC classification number: H01L23/66 ,  H01Q1/2283 ,  H01Q13/02 ,  H01L2223/6627 ,  H01L2223/6677

    Abstract: In some examples, a semiconductor package includes a semiconductor die; a conductive member coupled to the semiconductor die; and a multi-layer package substrate. The multi-layer package substrate includes a first horizontal metal layer to provide a ground connection; a second horizontal metal layer above the first horizontal metal layer; vertical members coupling to the first and second horizontal metal layers; and a mold compound covering the first and second horizontal metal layers and the vertical members. The first horizontal metal layer, the second horizontal metal layer, and the vertical members together form a structure including a conductive strip coupled to the conductive member, a transition member coupled to the conductive strip, a waveguide coupled to the transition member, and a horn antenna coupled to the waveguide.

    INTERDIGITAL CAPACITOR
    16.
    发明公开
    INTERDIGITAL CAPACITOR 审中-公开

    公开(公告)号：US20230402356A1

    公开(公告)日：2023-12-14

    申请号：US17838797

    申请日：2022-06-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yiqi TANG ,  Rajen Manicon MURUGAN

    IPC: H01L23/495 ,  H01L23/48 ,  H01L21/48

    CPC classification number: H01L23/49589 ,  H01L23/481 ,  H01L21/4821 ,  H01L23/49548 ,  H01L23/49586

    Abstract: A routable lead frame (RLF) substrate has a conductive layer having first- and second-side traces having first fingers and second fingers, respectively, which are interdigitated with each other. A via layer is over the conductive layer. A first-side conductive via of the via layer is conductively coupled to the first-side trace. A second-side conductive via of the via layer is conductively coupled to the second-side trace. Dielectric molding material is disposed between the interdigitated fingers of the conductive layer and between the first-side conductive via and the second-side conductive via. The fingers and vias form an interdigital capacitor (IDC) useful in impedance matching and filtering.

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