公开(公告)号：US20190325109A1

公开(公告)日：2019-10-24

申请号：US16458852

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng LIN ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Shih-Wei PENG ,  Wei-Chen CHIEN

IPC: G06F17/50

Abstract: A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.

公开(公告)号：US20180151559A1

公开(公告)日：2018-05-31

申请号：US15782183

申请日：2017-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Yi-Hsun CHIU

IPC: H01L27/085 ,  H01L27/118

Abstract: An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants.

公开(公告)号：US20180151552A1

公开(公告)日：2018-05-31

申请号：US15676225

申请日：2017-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Ko-Bin KAO ,  Ru-Gun LIU ,  Shun Li CHEN

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L27/0207 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/41791 ,  H01L29/42376

Abstract: A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different.

公开(公告)号：US20240021516A1

公开(公告)日：2024-01-18

申请号：US18356354

申请日：2023-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L21/76804 ,  H01L23/528

Abstract: An integrated circuit includes a substrate; and a first conductive line extending parallel to a top surface of the substrate. The first conductive line is a first distance from the substrate. The integrated circuit further includes a second conductive line extending parallel to the top surface of the substrate. The second conductive line is a second distance from the substrate. The integrated circuit further includes a third conductive line extending parallel to the top surface of the substrate. The third conductive line is a third distance from the substrate. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line, wherein a first angle between a sidewall of a lower portion of the supervia and the substrate is different from a second angle between a sidewall of an upper portion of the supervia and the substrate.

公开(公告)号：US20230154846A1

公开(公告)日：2023-05-18

申请号：US18156752

申请日：2023-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Wei-An LAI ,  Meng-Hung SHEN ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG ,  Kam-Tou SIO

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L21/76877 ,  H01L21/76831 ,  H01L21/76802

Abstract: A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.

公开(公告)号：US20220360263A1

公开(公告)日：2022-11-10

申请号：US17872490

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Jiun-Wei LU

IPC: H03K19/17736 ,  H03K19/17784 ,  G06F1/10

Abstract: An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

公开(公告)号：US20220254769A1

公开(公告)日：2022-08-11

申请号：US17317708

申请日：2021-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell.

公开(公告)号：US20220108990A1

公开(公告)日：2022-04-07

申请号：US17552433

申请日：2021-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Chin-Yuan TSENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Wei-Liang LIN ,  L. C. CHOU

IPC: H01L27/11 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.

公开(公告)号：US20210286927A1

公开(公告)日：2021-09-16

申请号：US17332646

申请日：2021-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  G03F1/36 ,  G06F30/394

Abstract: A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.

公开(公告)号：US20210118868A1

公开(公告)日：2021-04-22

申请号：US17132447

申请日：2020-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Yi-Hsun CHIU

IPC: H01L27/02 ,  H01L27/085 ,  H01L27/092 ,  H01L27/118

Abstract: An integrated circuit structure includes a first well, a second well, a third well, a first set of implants and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion of the first well, extending in the first direction and having a second width. The second well has a second dopant type and is adjacent to the first well. The third well has the second dopant type, and is adjacent to the first well. The first portion of the first well is between the second well and the third well. The first set of implants is in the first portion of the first well, the second well and the third well. The second set of implants is in the second portion of the first well.