公开(公告)号：US20230064444A1

公开(公告)日：2023-03-02

申请号：US17461363

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Fu YEH ,  Chin-Lung CHUNG ,  Shu-Wei LI ,  Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/532

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

公开(公告)号：US20220165617A1

公开(公告)日：2022-05-26

申请号：US16949953

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guanyu LUO ,  Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285

Abstract: A method includes receiving an integrated circuit (IC) layout having a plurality of metal features in a metal layer. The method also includes classifying the plurality of metal features into a first type of metal features and a second type of metal features based on a dimensional criterion, where the first type of the metal features have dimensions greater than the second type of the metal features. The method further includes assigning to the first type of metal features a first metal material, and to the second type of metal features a second metal material, where the second metal material is different from the first metal material. The method additionally includes forming the plurality of metal features embedded within a dielectric layer, where each of the plurality of metal features have the respective assigned metal materials.

公开(公告)号：US20240387251A1

公开(公告)日：2024-11-21

申请号：US18786475

申请日：2024-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.

公开(公告)号：US20240363534A1

公开(公告)日：2024-10-31

申请号：US18770940

申请日：2024-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Guanyu LUO ,  Ming-Han LEE ,  Shin-Yi YANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76843 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53238

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.

公开(公告)号：US20240006233A1

公开(公告)日：2024-01-04

申请号：US17855433

申请日：2022-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L23/5226 ,  H01L23/53247 ,  H01L23/53252 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877

Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.

公开(公告)号：US20230378077A1

公开(公告)日：2023-11-23

申请号：US18230546

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Han LEE ,  Shin-Yi YANG ,  Shau-Lin SHUE

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L23/5385 ,  H01L25/105 ,  H01L25/50 ,  H01L24/16 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49816 ,  H01L2924/1431 ,  H01L2225/1023 ,  H01L2924/1434 ,  H01L2224/16225 ,  H01L2225/1041 ,  H01L2224/16146 ,  H01L2225/1058

Abstract: Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.

公开(公告)号：US20230062128A1

公开(公告)日：2023-03-02

申请号：US17460537

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shu-Wei LI ,  Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.

公开(公告)号：US20220375791A1

公开(公告)日：2022-11-24

申请号：US17875953

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guanyu LUO ,  Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45 ,  H01L23/522

Abstract: A semiconductor device includes a first underlying metal line and a second underlying metal line in a first dielectric layer over a substrate. The semiconductor device includes a first metal feature and a second metal feature in a second dielectric layer over the first dielectric layer. The first metal feature is over and connected to the first underlying metal line, and the second metal feature is over and connected to the second underlying metal line. The first metal feature has a first dimension, the second metal feature has a second dimension, the second dimension being greater than the first dimension. The first metal feature includes a first metal having a first mean free path, the second metal feature includes a second metal having a second mean free path, and the second mean free path is greater than the first mean free path.

公开(公告)号：US20240203789A1

公开(公告)日：2024-06-20

申请号：US18591384

申请日：2024-02-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Fu YEH ,  Chin-Lung CHUNG ,  Shu-Wei LI ,  Yu-Chen CHAN ,  Shin-Yi YANG ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/7684 ,  H01L21/76844 ,  H01L23/53276 ,  H01L21/76846

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

公开(公告)号：US20240071822A1

公开(公告)日：2024-02-29

申请号：US17900151

申请日：2022-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-Lung CHUNG ,  Shin-Yi YANG ,  Yu-Chen CHAN ,  Han-Tang HUNG ,  Shu-Wei LI ,  Ming-Han LEE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/53238

Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.