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    Method for forming interconnect structure
    12.
    发明授权
    Method for forming interconnect structure 有权

    公开(公告)号：US10741417B2

    公开(公告)日：2020-08-11

    申请号：US15828077

    申请日：2017-11-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

    IPC分类号： H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

    摘要： A method for forming an interconnect structure is provided. The method includes: forming a dielectric layer on a substrate, and forming an opening in the dielectric layer; forming a first metal layer, a second metal layer, and a third metal layer sequentially over the dielectric layer. The opening of the dielectric layer is filled with the first metal layer to form a conductive via. The method also includes: performing one or multiple etch operation to etch the first metal layer, the second metal layer, and the third metal layer, so as to form a metal line corresponding to the first metal layer, an intermediate metal layer corresponding to the second metal layer, and a metal pillar corresponding to the third metal layer. In particular, the width of the metal line is greater than the width of the metal pillar.

    Semiconductor device
    16.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11854836B2

    公开(公告)日：2023-12-26

    申请号：US18161701

    申请日：2023-01-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

    IPC分类号： H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L21/486 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14

    摘要： An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

    Memory device and fabrication method thereof
    20.
    发明授权
    Memory device and fabrication method thereof 有权

    公开(公告)号：US10700264B2

    公开(公告)日：2020-06-30

    申请号：US16511862

    申请日：2019-07-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

    IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

    摘要： A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.