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公开(公告)号：US10424666B2
公开(公告)日：2019-09-24
申请号：US15680034
申请日：2017-08-17
Applicant: Silanna Asia Pte Ltd
Inventor： Shanghui Larry Tu , Michael A. Stuber , Befruz Tasbas , Stuart B. Molin , Raymond Jiang
IPC: H01L29/786 , H01L29/10 , H01L27/12 , H01L29/78 , H01L29/06 , H01L21/84 , H01L21/74 , H01L29/66 , H01L21/48 , H01L21/768 , H01L23/48 , H01L23/495 , H01L23/00 , H01L29/417 , H01L23/522 , H01L23/535 , H01L25/00 , H01L23/485
Abstract: A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip (“clip”), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.
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12.发明申请公开(公告)号：US20180240737A1
公开(公告)日：2018-08-23
申请号：US15640081
申请日：2017-06-30
Applicant: Silanna Asia Pte Ltd
Inventor： Shanghui Larry Tu , Michael A. Stuber , Befruz Tasbas , Stuart B. Molin , Raymond Jiang
IPC: H01L23/495 , H01L27/088 , H01L21/8234 , H01L29/78
CPC classification number: H01L23/49517 , H01L21/823475 , H01L27/088 , H01L29/66681 , H01L29/7816
Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
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公开(公告)号：US20170207177A1
公开(公告)日：2017-07-20
申请号：US14997942
申请日：2016-01-18
Applicant: Silanna Asia Pte Ltd.
Inventor： Stuart B. Molin , George Imthurn
IPC: H01L23/552 , H01L29/06 , H01L29/10 , H01L29/08 , H01L21/768 , H01L29/78 , H01L23/528 , H01L29/66 , H01L29/45
CPC classification number: H01L23/552 , H01L21/76895 , H01L23/528 , H01L29/0649 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/402 , H01L29/41733 , H01L29/4175 , H01L29/45 , H01L29/66681 , H01L29/66696 , H01L29/66772 , H01L29/7816 , H01L29/7824 , H01L29/78624 , H01L29/78639 , H01L29/78654
Abstract: A quasi-lateral diffusion transistor is formed in a semiconductor-on-insulator (SOI) wafer by forming a gate region, a body region, a drift region, and a source region and bonding a handle wafer to the SOI wafer at a first side (e.g., top side) of the SOI wafer; and removing a semiconductor substrate of the SOI wafer, forming a hole in a buried insulator layer of the SOI wafer, and forming a drain region for the transistor at a second side (e.g., bottom side) of the SOI wafer. The body region and the drift region physically contact the buried insulator layer. The drain region is formed in a bottom portion of the drift region exposed by the hole and is laterally offset from the source region. In operation of the quasi-lateral diffusion transistor, a current flow direction through the semiconductor layer is diagonal between the source region and the drain region.
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公开(公告)号：US11855615B2
公开(公告)日：2023-12-26
申请号：US18166793
申请日：2023-02-09
Applicant: Silanna Asia Pte Ltd
Inventor： Joseph H. Colles , Steven E. Rosenbaum , Stuart B. Molin
CPC classification number: H03K17/145 , H02M1/08 , H02M1/38 , H02M3/158 , H03K5/133 , H03K21/38 , H03K2005/00019 , H03K2005/00078 , H03K2005/00247
Abstract: An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.
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公开(公告)号：US20230188132A1
公开(公告)日：2023-06-15
申请号：US18166793
申请日：2023-02-09
Applicant: Silanna Asia Pte Ltd
Inventor： Joseph H. Colles , Steven E. Rosenbaum , Stuart B. Molin
CPC classification number: H03K17/145 , H02M1/08 , H02M1/38 , H02M3/158 , H03K5/133 , H03K21/38 , H03K2005/00247
Abstract: An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.
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Patent Agency Ranking
公开(公告)号：US11611337B2
公开(公告)日：2023-03-21
申请号：US16949304
申请日：2020-10-23
Applicant: Silanna Asia Pte Ltd
Inventor： Joseph H. Colles , Steven E. Rosenbaum , Stuart B. Molin
Abstract: An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.
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公开(公告)号：US20220416775A1
公开(公告)日：2022-12-29
申请号：US17823019
申请日：2022-08-29
Applicant: Silanna Asia Pte Ltd
Inventor： Joseph H. Colles , Steven E. Rosenbaum , Stuart B. Molin
IPC: H03K5/134
Abstract: In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.
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18.发明申请公开(公告)号：US20220278027A1
公开(公告)日：2022-09-01
申请号：US17660721
申请日：2022-04-26
Applicant: Silanna Asia Pte Ltd
Inventor： Shanghui Larry Tu , Michael A. Stuber , Befruz Tasbas , Stuart B. Molin , Raymond Jiang
IPC: H01L23/495 , H01L29/78 , H01L29/66 , H01L29/786 , H01L29/06 , H01L29/417 , H01L27/12 , H01L23/535
Abstract: A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
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公开(公告)号：US11424717B2
公开(公告)日：2022-08-23
申请号：US16938294
申请日：2020-07-24
Applicant: Silanna Asia Pte Ltd
Inventor： Steven E. Rosenbaum , Stuart B. Molin
Abstract: A closed-loop switch-mode boost converter includes a switching signal generator circuit, a switch-mode boost amplifier, a filter circuit, and an error amplifier circuit. The switching signal generator circuit receives an input signal and outputs a switching signal. A duty-cycle of the switching signal has a first non-linear relationship to an amplitude of the input signal. The switch-mode boost amplifier receives the switching signal and produces an output signal. An amplitude of the output signal has a second non-linear relationship to the duty-cycle of the switching signal, and the output signal has a linear relationship to the input signal based on the first and second non-linear relationships. The filter circuit receives the output signal and outputs a filtered output signal. The error amplifier circuit receives the input signal and the filtered output signal and produces a feedback control signal. The filtered output signal is adjusted based on the feedback control signal.
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公开(公告)号：US20220149588A1
公开(公告)日：2022-05-12
申请号：US17648907
申请日：2022-01-25
Applicant: Silanna Asia Pte Ltd
Inventor： Joseph H. Colles , Steven E. Rosenbaum , Stuart B. Molin
Abstract: A pulsed laser diode driver includes an inductor having a first terminal configured to receive a source voltage. A source capacitor has a first terminal connected to the first terminal of the inductor to provide the source voltage. A bypass switch has a drain node connected to a second terminal of the inductor and to a first terminal of a bypass capacitor. A laser diode switch has a drain node connected to the second terminal of the inductor. A laser diode has an anode connected to a source node of the laser diode switch and a cathode connected to a bias voltage node. The laser diode switch and the bypass switch control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.
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