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公开(公告)号：US11894656B2
公开(公告)日：2024-02-06
申请号：US17653349
申请日：2022-03-03
申请人： Silanna Asia Pte Ltd
IPC分类号： H01S5/042 , H03K17/687 , H03K19/20
CPC分类号： H01S5/0428 , H03K17/6871 , H03K19/20
摘要： A pulsed laser diode driver includes a refresh circuit configured to generate a refresh current using a received input voltage. A current amplitude of the refresh current is controlled by the refresh circuit based on a voltage level of a source voltage received by the refresh circuit. A source capacitor of the pulsed laser diode driver is configured to receive the refresh current and to develop the source voltage therefrom. An inductor of the pulsed laser diode driver has a first terminal that is directly electrically connected to the source capacitor. One or more switches of the pulsed laser diode driver are configured to control a current flow through the inductor to produce a high-current pulse through a laser diode that corresponds to a peak current of a resonant waveform developed at an anode of the laser diode.
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公开(公告)号：US20230198225A1
公开(公告)日：2023-06-22
申请号：US18167164
申请日：2023-02-10
申请人： Silanna Asia Pte Ltd
CPC分类号： H01S5/0428 , H01S5/0261 , H01S5/06808 , H01S5/423
摘要： A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.
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公开(公告)号：US11552558B2
公开(公告)日：2023-01-10
申请号：US17303949
申请日：2021-06-10
申请人： Silanna Asia Pte Ltd
IPC分类号： H02M3/07 , H03K17/687 , H02M1/088 , H02M1/00
摘要： A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.
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公开(公告)号：US11451220B2
公开(公告)日：2022-09-20
申请号：US17454207
申请日：2021-11-09
申请人： Silanna Asia Pte Ltd
摘要： In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.
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公开(公告)号：US11444433B2
公开(公告)日：2022-09-13
申请号：US17446606
申请日：2021-08-31
申请人： Silanna Asia Pte Ltd
IPC分类号： H01S5/026 , H01S5/042 , H01S5/0233 , H03K17/687 , H01S5/42 , H01S5/40
摘要： A laser diode driver includes a clock terminal to receive a clock signal, configuration terminals to receive configuration data, drive terminals, and charging terminals. A first charging terminal is operable to charge a source capacitor of a resonant circuit that includes the source capacitor, an inductor, and a bypass capacitor. Each drive terminal is operable to be directly electrically connected to an anode or cathode of a laser diode or to ground. A mode, output selection, and grouping of drive signals that are delivered to the laser diodes are configured based on the configuration data. The laser diode driver is operable to control a current flow through the resonant circuit to produce high-current pulses through the laser diodes, the high-current pulses corresponding to a peak current of a resonant waveform developed at respective anodes of the laser diodes, a timing of the high-current pulses being synchronized using the clock signal.
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公开(公告)号：US20220166418A1
公开(公告)日：2022-05-26
申请号：US17454207
申请日：2021-11-09
申请人： Silanna Asia Pte Ltd
IPC分类号： H03K5/134
摘要： In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.
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公开(公告)号：US11335627B2
公开(公告)日：2022-05-17
申请号：US16737524
申请日：2020-01-08
申请人： Silanna Asia Pte Ltd
IPC分类号： H01L23/495 , H01L29/78 , H01L29/66 , H01L29/786 , H01L29/06 , H01L29/417 , H01L27/12 , H01L23/535 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/40
摘要： A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
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公开(公告)号：US10855270B1
公开(公告)日：2020-12-01
申请号：US16600857
申请日：2019-10-14
申请人： Silanna Asia Pte Ltd
摘要： An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.
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公开(公告)号：US20200258988A1
公开(公告)日：2020-08-13
申请号：US16859154
申请日：2020-04-27
申请人： Silanna Asia Pte Ltd
摘要： An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.
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10.发明授权公开(公告)号：US10546804B2
公开(公告)日：2020-01-28
申请号：US16137300
申请日：2018-09-20
申请人： Silanna Asia Pte Ltd
IPC分类号： H01L23/495 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L27/088
摘要： A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
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