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公开(公告)号:US11044784B2
公开(公告)日:2021-06-22
申请号:US16352122
申请日:2019-03-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Youngsung Kho , Kyuho Han , Joonseo Lee , Moonyoung Jeong , Giwon Lee
Abstract: A method of a first terminal is provided. The method includes communicating with a first gateway by using a first internet protocol (IP) address allocated to the first terminal, according to a first IP session, in response to a distance between the first terminal and a second gateway being equal to or less than a predetermined threshold, establishing a second IP session with the second gateway while the first IP session is set in the first terminal, receiving, from a second terminal, a first IP session-release message about the first IP session via the second gateway by using a second IP address according to the second IP session, when data from the first terminal is received by the second terminal according to the first IP session, and in response to the first IP session-release message being received from the second gateway, releasing the first IP session with the first gateway.
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公开(公告)号:US10325992B2
公开(公告)日:2019-06-18
申请号:US14854272
申请日:2015-09-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunae Cho , Dongjin Lee , Ji Eun Lee , Kyoung-Ho Jung , Dong Su Ko , Yongsu Kim , Jiho Yoo , Sung Heo , Hyun Park , Satoru Yamada , Moonyoung Jeong , Sungjin Kim , Gyeongsu Park , Han Jin Lim
IPC: H01L29/423 , H01L29/49 , H01L21/28 , H01L29/51
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
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公开(公告)号:US09905659B2
公开(公告)日:2018-02-27
申请号:US15011820
申请日:2016-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongjin Lee , Junsoo Kim , Moonyoung Jeong , Satoru Yamada , Dongsoo Woo , Jiyoung Kim
IPC: H01L29/40 , H01L29/423 , H01L27/108 , H01L27/088
CPC classification number: H01L29/402 , H01L27/088 , H01L27/10876 , H01L29/42392
Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
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公开(公告)号:US20230345696A1
公开(公告)日:2023-10-26
申请号:US18132198
申请日:2023-04-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhan Park , Bowon Yoo , Hyunseo Shin , Kiseok Lee , Moonyoung Jeong
IPC: H10B12/00
CPC classification number: H10B12/0387 , H10B12/0383 , H10B12/488
Abstract: A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate. A plurality of first filling layers is formed that fills the first trenches and have protrusions extending to protrude from the substrate. Spacers are formed on sidewalls of the protrusions of the first filling layers. The spacers expose portions of the substrate between adjacent first filling layers. A plurality of second trenches is formed around the first trenches by etching the portions of the substrate exposed by the spacers. A plurality of second filling layers is formed that fills the second trenches. All of the first filling layers and the spacers are removed. A gate material layer is formed that conformally covers inner walls of the first trenches. A pair of gate structures is formed in each of the first trenches by separating the gate material layer.
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公开(公告)号:US11735637B2
公开(公告)日:2023-08-22
申请号:US17400901
申请日:2021-08-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunae Cho , Dongjin Lee , Ji Eun Lee , Kyoung-Ho Jung , Dong Su Ko , Yongsu Kim , Jiho Yoo , Sung Heo , Hyun Park , Satoru Yamada , Moonyoung Jeong , Sungjin Kim , Gyeongsu Park , Han Jin Lim
IPC: H01L29/423 , H01L29/49 , H01L21/28 , H01L29/51
CPC classification number: H01L29/4236 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
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公开(公告)号:US20230180468A1
公开(公告)日:2023-06-08
申请号:US18052689
申请日:2022-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiseok Lee , Moonyoung Jeong , Jong-Ho Moon , Han-Sik Yoo , Keunnam Kim , Hyungeun Choi
IPC: H01L27/108 , H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00
CPC classification number: H01L27/10897 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L25/0657 , H01L27/10805 , H01L27/10894 , H01L2224/06515 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436
Abstract: A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.
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公开(公告)号:US11229080B2
公开(公告)日:2022-01-18
申请号:US16259443
申请日:2019-01-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Giwon Lee , Moonyoung Jeong , Youngsung Kho , Joonseo Lee , Kyuho Han
Abstract: Provided are a method and apparatus for managing a session in a wireless communication system. The method includes identifying a session management module with a failure from among a plurality of session management modules that each manage at least one session; determining a substitute module that replaces the session management module with the failure; obtaining, from a control plane entity, information about at least one session managed by the session management module with the failure; and controlling the substitute module to manage the at least one session, based on the obtained information about the at least one session.
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公开(公告)号:US11127828B2
公开(公告)日:2021-09-21
申请号:US16432298
申请日:2019-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunae Cho , Dongjin Lee , Ji Eun Lee , Kyoung-Ho Jung , Dong Su Ko , Yongsu Kim , Jiho Yoo , Sung Heo , Hyun Park , Satoru Yamada , Moonyoung Jeong , Sungjin Kim , Gyeongsu Park , Han Jin Lim
IPC: H01L29/423 , H01L29/49 , H01L21/28 , H01L29/51
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
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公开(公告)号:US20200027885A1
公开(公告)日:2020-01-23
申请号:US16588360
申请日:2019-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongjin Lee , Ji-Eun Lee , Kyoung-Ho Jung , Satoru Yamada , Moonyoung Jeong
IPC: H01L27/108 , H01L21/28 , H01L29/49
Abstract: Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.
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公开(公告)号:US10263084B2
公开(公告)日:2019-04-16
申请号:US15868620
申请日:2018-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongjin Lee , Junsoo Kim , Moonyoung Jeong , Satoru Yamada , Dongsoo Woo , Jiyoung Kim
IPC: H01L29/40 , H01L29/423 , H01L27/108 , H01L27/088
Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
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