公开(公告)号：US12125909B2

公开(公告)日：2024-10-22

申请号：US17584580

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsung Woo ,  Changmin Jeon ,  Yongkyu Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/7835 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78624 ,  H01L29/66492

Abstract: A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.

公开(公告)号：US11950423B2

公开(公告)日：2024-04-02

申请号：US17306308

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkyu Lee ,  Youngmok Kim ,  Changmin Jeon ,  Yongsang Jeong

IPC: H01L27/11573 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/40 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.

公开(公告)号：US20240006195A1

公开(公告)日：2024-01-04

申请号：US18296336

申请日：2023-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNSEOK Choi ,  Eunseok Lee ,  Seungri Ju ,  Yungjun Kim ,  Jaehyun Sung ,  Yongkyu Lee

IPC: H01L21/67 ,  H01L21/02

CPC classification number: H01L21/67051 ,  H01L21/02057

Abstract: A wafer cleaning equipment includes a vessel that includes a first inner wall, a second inner wall that faces the first inner wall, and a bottom connected to the first and second inner walls, a plurality of first nozzles disposed on the first inner wall, a plurality of second nozzles disposed on the second inner wall, a support structure disposed between the plurality of first nozzles and the plurality of second nozzles, where the support structure supports a wafer, and a megasonic cleaner disposed between the bottom of the vessel and the wafer supported by the support structure. The megasonic cleaner includes a rack and at least one vibrator disposed below the rack.

公开(公告)号：US11380386B2

公开(公告)日：2022-07-05

申请号：US17147557

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Woong Lee ,  Doo-Ho Cho ,  Sang Soo Park ,  Yongkyu Lee

IPC: G11C16/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/04 ,  G11C16/34 ,  G11C16/32 ,  G11C16/28

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array that includes a plurality of memory cells, a page buffer circuit that is connected with the memory cell array through a plurality of bit lines and performs a sensing operation of sensing memory cells selected from the plurality of memory cells through the plurality of bit lines during a sensing time, an input/output circuit that performs a data output operation of outputting data from the page buffer circuit to an external device through data lines, and a sensing time control circuit that adjusts the sensing time when the data output operation is performed during the sensing time.

公开(公告)号：US20220085048A1

公开(公告)日：2022-03-17

申请号：US17306308

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkyu Lee ,  Youngmok Kim ,  Changmin Jeon ,  Yongsang Jeong

IPC: H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.