公开(公告)号：US20180122811A1

公开(公告)日：2018-05-03

申请号：US15614077

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEIK KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  BONG-SOO KIM ,  JEMIN PARK ,  CHAN-SIC YOON ,  YOOSANG HWANG

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894

Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.

公开(公告)号：US20230253315A1

公开(公告)日：2023-08-10

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  KEUNNAM KIM ,  SOHYUN PARK ,  JIN-HWAN CHUN ,  WOOYOUNG CHOI ,  SUNGHEE HAN ,  INKYOUNG HEO ,  YOOSANG HWANG

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L29/0649 ,  G11C5/10 ,  H01L29/4236 ,  H01L21/76831 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20210273048A1

公开(公告)日：2021-09-02

申请号：US16996282

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJIN PARK ,  CHULKWON PARK ,  SOYEONG KIM ,  EUN A KIM ,  HYO-SUB KIM ,  SOHYUN PARK ,  SUNGHEE HAN ,  YOOSANG HWANG

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/28 ,  H01L29/41

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

公开(公告)号：US20210159277A1

公开(公告)日：2021-05-27

申请号：US17167851

申请日：2021-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUI-JUNG KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  YOOSANG HWANG

IPC: H01L27/24 ,  H01L45/00

Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

公开(公告)号：US20210143154A1

公开(公告)日：2021-05-13

申请号：US17126195

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20200006434A1

公开(公告)日：2020-01-02

申请号：US16455791

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUI-JUNG KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  YOOSANG HWANG

IPC: H01L27/24 ,  H01L45/00

Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

公开(公告)号：US20170125283A1

公开(公告)日：2017-05-04

申请号：US15334469

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.