公开(公告)号：US09520300B2

公开(公告)日：2016-12-13

申请号：US14606970

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wookyung You ,  Jongmin Baek ,  Sanghoon Ahn ,  Sangho Rha ,  Naein Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20150187699A1

公开(公告)日：2015-07-02

申请号：US14503877

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括导电图案之间的间隙。 此外，半导体器件在导电图案上包括可渗透层。 还提供了制造半导体器件的方法。

公开(公告)号：US20240203872A1

公开(公告)日：2024-06-20

申请号：US18590793

申请日：2024-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun Lim ,  Wookyung You ,  Kyoungwoo Lee ,  Juyoung Jung ,  Il Sup Kim ,  Chin Kim ,  Kyoungpil Park ,  Jinhyung Park

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06

CPC classification number: H01L23/5228 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L27/0688

Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

公开(公告)号：US11948883B2

公开(公告)日：2024-04-02

申请号：US17221191

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun Lim ,  Wookyung You ,  Kyoungwoo Lee ,  Juyoung Jung ,  Il Sup Kim ,  Chin Kim ,  Kyoungpil Park ,  Jinhyung Park

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L27/0688

Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

公开(公告)号：US20240085812A1

公开(公告)日：2024-03-14

申请号：US18230472

申请日：2023-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuhee Han ,  Koungmin Ryu ,  Kyeongbeom Park ,  Jongmin Baek ,  Wookyung You ,  Woojin Lee ,  Juhee Lee

IPC: G03F7/00 ,  G03F7/20 ,  G03F7/40 ,  H01L21/033

CPC classification number: G03F7/70925 ,  G03F7/2004 ,  G03F7/40 ,  H01L21/033

Abstract: A substrate processing apparatus includes a chamber having an internal space configured to process a substrate loaded therein; a light source configured to emit light on the substrate to harden a photoresist pattern coated on the substrate; and a transparent division part provided between the substrate and the light source, wherein the transparent division part divides the chamber into a first space, in which the light source is provided, and a second space, in which the substrate is provided.

公开(公告)号：US11424182B2

公开(公告)日：2022-08-23

申请号：US17130293

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US10269712B2

公开(公告)日：2019-04-23

申请号：US15927270

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/288 ,  H01L21/321

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US09842803B2

公开(公告)日：2017-12-12

申请号：US15375567

申请日：2016-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

公开(公告)号：US09711453B2

公开(公告)日：2017-07-18

申请号：US15155539

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20170178949A1

公开(公告)日：2017-06-22

申请号：US15374053

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Thomas Oszinda ,  Jongmin Baek ,  Sanghoon Ahn ,  Byunghee Kim ,  Wookyung You ,  Naein Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.