公开(公告)号：US10153050B2

公开(公告)日：2018-12-11

申请号：US15822320

申请日：2017-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hyun Kim ,  Bong-Soon Lim ,  Yoon-Hee Choi ,  Sang-Won Shim

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.

公开(公告)号：US09595612B2

公开(公告)日：2017-03-14

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US09184232B2

公开(公告)日：2015-11-10

申请号：US14538046

申请日：2014-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US20130320461A1

公开(公告)日：2013-12-05

申请号：US13960434

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HWAN KIM ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.