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    Electronic device for seamlessly displaying images, and operating method therefor
    11.
    发明授权
    Electronic device for seamlessly displaying images, and operating method therefor 有权

    公开(公告)号：US12118262B2

    公开(公告)日：2024-10-15

    申请号：US17703347

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjin Kim ,  Sungjun Lee ,  Jungbae Kim ,  Joonyung Park ,  Jiesoon Jeong ,  Mooyoung Kim

    IPC: G06T3/40 ,  G06F3/14 ,  G06T3/60

    CPC classification number: G06F3/1423 ,  G06T3/40 ,  G06T3/60

    Abstract: An electronic device is provided. The electronic device includes a first display disposed on a first surface of the electronic device, a second display disposed on a second surface of the electronic device and having at least a portion thereof being unviewable to a user according to a folding state of the electronic device, a memory configured to store instructions, and a processor electrically connected to the first display, the second display, and the memory. The processor is configured to execute the instructions to detect a change in the folding state of the electronic device while displaying a first image on one of the first display or the second display, when the change in the folding state is detected, generate a second image to be displayed on the other of the first display or the second display, while generating the second image, store a snapshot image of the first image in the memory and display the snapshot image on the other of the first display or the second display, and when the second image is generated, display the second image on the other of the first display or the second display instead of the snapshot image.

    Electronic device and method for controlling timing signal
    15.
    发明授权
    Electronic device and method for controlling timing signal 有权

    公开(公告)号：US11380286B2

    公开(公告)日：2022-07-05

    申请号：US17155132

    申请日：2021-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gwanghui Lee ,  Minwoo Kim ,  Seungjin Kim ,  Minwoo Lee ,  Juseok Lee ,  Woojun Jung

    IPC: G09G5/36 ,  G09G5/18 ,  G09G5/12

    Abstract: According to an embodiment, an electronic device may include at least one processor, a display, a memory configured to store image frames, and a display controller configured to output the image frames. The at least one processor may be configured to transmit a first image frame to be output through the display, based on a first timing signal received from the display controller, identify a state of the electronic device, transmit first control information for changing a timing of the first timing signal, in response to transmitting the first control information for changing the timing of the first timing signal, receive a second timing signal from the display controller, and transmit, to the memory, a second image frame to be output through the display, based on the received second timing signal. The timing of the second timing signal may differ from the timing of the first timing signal.

    Oscillator using sampling PLL-based injection
    16.
    发明授权
    Oscillator using sampling PLL-based injection 有权

    公开(公告)号：US11876487B2

    公开(公告)日：2024-01-16

    申请号：US18152418

    申请日：2023-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehong Jung ,  Seungjin Kim ,  Seunghyun Oh

    IPC: H03B5/36 ,  H03L7/099

    CPC classification number: H03B5/36 ,  H03L7/099 ,  H03B2200/009

    Abstract: An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

    OSCILLATOR USING SAMPLING PLL-BASED INJECTION
    17.
    发明公开
    OSCILLATOR USING SAMPLING PLL-BASED INJECTION 审中-公开

    公开(公告)号：US20230291354A1

    公开(公告)日：2023-09-14

    申请号：US18152418

    申请日：2023-01-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehong JUNG ,  Seungjin Kim ,  Seunghyun Oh

    IPC: H03B5/36 ,  H03L7/099

    CPC classification number: H03B5/36 ,  H03L7/099 ,  H03B2200/009

    Abstract: An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

    Phase locked loop and operating method of phase locked loop
    19.
    发明授权
    Phase locked loop and operating method of phase locked loop 有权

    公开(公告)号：US11601131B2

    公开(公告)日：2023-03-07

    申请号：US17734693

    申请日：2022-05-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangdon Jung ,  Gyusik Kim ,  Seungjin Kim ,  Seunghyun Oh ,  Jihwan Kim

    IPC: H03L7/10 ,  H03L7/099 ,  H03L7/089

    Abstract: A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

    Automatic frequency calibration and lock detection circuit and phase locked loop including te same
    20.
    发明授权
    Automatic frequency calibration and lock detection circuit and phase locked loop including te same 有权

    公开(公告)号：US11496137B2

    公开(公告)日：2022-11-08

    申请号：US17536514

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Baekmin Lim ,  Seungjin Kim

    IPC: H03L7/095 ,  H03L7/099 ,  H03L7/089 ,  H03M7/16

    Abstract: An automatic frequency calibration and lock detection circuit includes a frequency error generator circuit, an automatic frequency calibration signal generator circuit, and a lock flag generator circuit. The frequency error generator circuit generates a frequency error signal based on a reference frequency signal and an output frequency signal. The frequency error signal represents a difference between a frequency of the output frequency signal and a target frequency. The automatic frequency calibration signal generator circuit generates an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal. The lock flag generator circuit generates a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal. The frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.

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