公开(公告)号：US10727246B2

公开(公告)日：2020-07-28

申请号：US15813556

申请日：2017-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Park ,  Jintaek Park

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L27/02 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L23/528 ,  H01L27/1157

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

公开(公告)号：USD805487S1

公开(公告)日：2017-12-19

申请号：US29568391

申请日：2016-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Jang-Ho Kim ,  Chul-Yong Cho ,  Sang-Yong Park ,  Ki-Hong Kim

公开(公告)号：USD788750S1

公开(公告)日：2017-06-06

申请号：US29564528

申请日：2016-05-13

Applicant: Samsung Electronics Co., Ltd.

Designer： Su-An Choi ,  Sang-Yong Park

公开(公告)号：US11925023B2

公开(公告)日：2024-03-05

申请号：US17726637

申请日：2022-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Park ,  Jintaek Park

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L27/02 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/31144 ,  H01L21/32139 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.

公开(公告)号：US10678556B2

公开(公告)日：2020-06-09

申请号：US16352185

申请日：2019-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Jang ,  Yae Seul Lee ,  Sang-Yong Park ,  Tae Sun You ,  Seong Wook Hwang

IPC: G06F1/3287 ,  G06F9/4401 ,  G06F1/324 ,  G06F1/3206 ,  G06F13/24 ,  G06F13/40 ,  G06F13/42

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

公开(公告)号：US10255079B2

公开(公告)日：2019-04-09

申请号：US15394518

申请日：2016-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Jang ,  Yae Seul Lee ,  Sang-Yong Park ,  Tae Sun You ,  Seong Wook Hwang

IPC: G06F9/00 ,  G06F9/4401 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/40 ,  G06F13/42

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

公开(公告)号：USD799442S1

公开(公告)日：2017-10-10

申请号：US29569166

申请日：2016-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Sang-Yong Park ,  Chul-Yong Cho ,  Ki-Hong Kim ,  Jang-Ho Kim

公开(公告)号：USD795850S1

公开(公告)日：2017-08-29

申请号：US29565894

申请日：2016-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Su-An Choi ,  Sang-Yong Park

公开(公告)号：USD777128S1

公开(公告)日：2017-01-24

申请号：US29567904

申请日：2016-06-14

Applicant: Samsung Electronics Co., Ltd.

Designer： Jang-Ho Kim ,  Chul-Yong Cho ,  Sang-Yong Park ,  Ki-Hong Kim

公开(公告)号：US09355913B2

公开(公告)日：2016-05-31

申请号：US14047578

申请日：2013-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Park ,  Jintaek Park ,  Hansoo Kim ,  Juhyuck Chung ,  Wonseok Cho

IPC: H01L21/82 ,  H01L21/44 ,  H01L29/792 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.