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11.发明授权公开(公告)号：US11798629B2
公开(公告)日：2023-10-24
申请号：US17489988
申请日：2021-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC: G11C7/14 , G11C16/10 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04 , H10B41/27 , H10B43/27
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/349 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B43/27 , H01L2224/05147 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US10153050B2
公开(公告)日：2018-12-11
申请号：US15822320
申请日：2017-11-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Hyun Kim , Bong-Soon Lim , Yoon-Hee Choi , Sang-Won Shim
Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.
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公开(公告)号：US09396800B2
公开(公告)日：2016-07-19
申请号：US14858120
申请日：2015-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Won Shim , Sang-Wan Nam , Kitae Park
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3427 , G11C16/3459
Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.
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公开(公告)号：US09142313B2
公开(公告)日：2015-09-22
申请号：US14060633
申请日：2013-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Won Shim , Sang-Wan Nam , Kitae Park
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3427 , G11C16/3459
Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.
Abstract translation: 提供了一种非易失性存储器件的编程方法，其包括以多个垂直字符串中选择的一个串中的存储器单元进行编程; 确定所述非易失存储器件的工作模式是否是预脉冲模式; 当操作模式被确定为预脉冲模式时，将具有预定电平的预脉冲施加到与多个垂直线中的至少一个未选择垂直弦的串选择晶体管的栅极连接的串选择线 特定时间段的字符串; 以及对所编程的存储单元执行验证操作。
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15.发明申请公开(公告)号：US20250087256A1
公开(公告)日：2025-03-13
申请号：US18418001
申请日：2024-01-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yoonjae Lee , Yeji Shin , Sang-Wan Nam , Sang-Won Shim
IPC: G11C7/10
Abstract: Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells, and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit including a first pump block, a second pump block, and a common pump block. The voltage generating circuit connects the first pump block and the common pump block in parallel to generate a first operating voltage among the plurality of operating voltages and connects the common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages. The common pump block is configurable to match the first pump block, the second pump block, or both, as needed.
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Patent Agency Ranking
公开(公告)号：US11854982B2
公开(公告)日：2023-12-26
申请号：US17982255
申请日：2022-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon Lim , Sang-Wan Nam , Sang-Won Park , Sang-Won Shim , Hongsoo Jeon , Yonghyuk Choi
IPC: H01L23/535 , H10B43/27 , H10B43/40
CPC classification number: H01L23/535 , H10B43/40
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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17.发明授权公开(公告)号：US11158379B2
公开(公告)日：2021-10-26
申请号：US16935535
申请日：2020-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC: G11C16/10 , G11C16/04 , G11C16/08 , G11C16/26 , G11C7/10 , G11C7/22 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11582 , H01L27/11556
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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18.发明申请公开(公告)号：US20210065806A1
公开(公告)日：2021-03-04
申请号：US16935535
申请日：2020-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
IPC: G11C16/10 , G11C16/04 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US20190080768A1
公开(公告)日：2019-03-14
申请号：US15908051
申请日：2018-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Shim
CPC classification number: G11C16/34 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/32 , G11C16/3418 , G11C16/3427 , G11C2211/5648
Abstract: A nonvolatile memory device for reducing hot-carrier injection (HCI) and a programming method of the nonvolatile memory device, the programming method of the nonvolatile memory device includes programming memory cells included in a cell string in a direction from an upper memory cell adjacent to a string selection transistor to a lower memory cell adjacent to a ground selection transistor from among a plurality of memory cells; when a selected memory cell is programmed, applying a first inhibition voltage to first non-selected word lines connected to first non-selected memory cells located over the selected memory cell; and applying a second inhibition voltage to second non-selected word lines connected to second non-selected memory cells located under the selected memory cell when a predetermined delay time elapses after the first inhibition voltage is applied.
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公开(公告)号：US09779790B2
公开(公告)日：2017-10-03
申请号：US15225017
申请日：2016-08-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Kitae Park , Sang-Won Shim
IPC: G11C8/08 , G11C5/02 , G11C16/04 , G11C16/30 , G11C16/10 , G11C16/08 , G11C8/10 , G11C7/04 , G11C11/56 , G11C16/32
CPC classification number: G11C8/08 , G11C5/02 , G11C7/04 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/32
Abstract: A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.
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