公开(公告)号：US20230378155A1

公开(公告)日：2023-11-23

申请号：US18156494

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Suhyeong Choi ,  Jiwook Kwon ,  Chulhong Park

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394

Abstract: A semiconductor device includes first standard cells arranged in a first row on a substrate and respectively including a first base active region, second standard cells arranged in a second row adjacent to the first row and respectively including a second base active region, a power line extending in a first direction along a boundary between the first and second standard cells, and a device isolation layer on side surfaces of the first and second base active regions, wherein, in a plan view, the first standard cells and the second standard cells have a same cell height, the first base active region of each of the first standard cells includes a first active line having a first conductivity-type and a second active line having a second conductivity-type, the second base active region of each of the second standard cells includes a third active line having the first conductivity-type and a fourth active line having the second conductivity-type, the first active lines of the first standard cells arranged in the first row have a same first width, the third active lines of the second standard cells arranged in the second row have a same second width, and the first width is narrower than the second width.

公开(公告)号：US11804480B2

公开(公告)日：2023-10-31

申请号：US17527432

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae Park ,  Byungju Kang ,  Yoonjeong Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/786 ,  H01L23/528 ,  B82Y10/00

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

公开(公告)号：US20230094036A1

公开(公告)日：2023-03-30

申请号：US17838551

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Subin Choi ,  Chulhong Park

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate electrode intersecting the active region and extending in a second direction, perpendicular to the first direction, a contact structure disposed on the active region on one side of the gate electrode and extending in the second direction, and a first via disposed on the contact structure to be connected to the contact structure and has a shape in which a length in the second direction is greater than a length in the first direction. A plurality of first metal interconnections are provided, which extend in the first direction on the first via, and are connected to the first via. A second via is provided, which is disposed on the plurality of first metal interconnections to be connected to the plurality of first metal interconnections and has a shape in which a length in the second direction is greater than a length in the first direction.

公开(公告)号：US10242984B2

公开(公告)日：2019-03-26

申请号：US15614911

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Sutae Kim ,  Donghyun Kim ,  Ha-Young Kim ,  Jung-ho Do ,  Sunyoung Park ,  Sanghoon Baek ,  Jaewan Choi

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.