公开(公告)号：US20250107071A1

公开(公告)日：2025-03-27

申请号：US18671624

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Keunui KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Gyuhwan OH ,  Bowon YOO ,  Kiseok LEE ,  Sangho LEE ,  Eunsuk JANG ,  Moonyoung JEONG

IPC: H10B12/00

Abstract: A semiconductor device comprising: a substrate; bit lines on the substrate; word lines on the bit lines, wherein the word lines are spaced apart from each other in a first direction; activation patterns between the word lines; a back gate electrode between the activation patterns, wherein the back gate electrode extends in a second direction; and a first gate separation pattern between the word lines in the first direction, wherein a portion of the word lines is a space between the activation patterns in the second direction and the word lines extend around the activation patterns, wherein the word lines and the first gate separation pattern each include a first surface facing the bit lines and a second surface opposite to the first surface in a third direction, wherein the first gate separation pattern is closer than the word lines to the bit lines in the third direction.

公开(公告)号：US20240130108A1

公开(公告)日：2024-04-18

申请号：US18369552

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Euichul JEONG ,  Sang-Woon LEE ,  Sangho LEE ,  Moonyoung JEONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

公开(公告)号：US20210037597A1

公开(公告)日：2021-02-04

申请号：US16965757

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsung KHO ,  Moonyoung JEONG ,  Jaehyun HWANG ,  Joonseo LEE ,  Kyuho HAN

IPC: H04W80/10 ,  H04W76/12 ,  H04W72/04

Abstract: Provided is a method of establishing a session for communication with a local network in a wireless communication system, the method including obtaining a request for using an integrated mode in which a user plane entity of a base station uses an integrated user plane entity that performs an operation of a user plane function (UPF) together, when a session between a local network and a user equipment (UE) is established, determining based on user information of the UE whether to accept use of an integrated mode, selecting the integrated user plane entity as a user plane entity in which the session is to be established, based on a result of the determining, and transmitting a session establishment request to the selected integrated user plane entity.

公开(公告)号：US20160240619A1

公开(公告)日：2016-08-18

申请号：US15011820

申请日：2016-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/402 ,  H01L27/088 ,  H01L27/10876 ,  H01L29/42392

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

Abstract translation: 半导体器件可以包括被配置为在衬底中限定有源区的器件隔离区，设置在有源区中的有源栅极结构以及设置在器件隔离区中的场栅结构。 场栅结构可以包括栅极导电层。 有源栅极结构可以包括上有源栅极结构，其包括形成在上有源栅极结构下方并与上有源栅极结构垂直间隔开的栅极导电层和下有源栅极结构。 下部有源栅极结构可以包括栅极导电层。 场栅结构的栅极导电层的顶表面位于比上有源栅极结构的栅极导电层的底表面更低的水平处。

公开(公告)号：US20250126775A1

公开(公告)日：2025-04-17

申请号：US18635612

申请日：2024-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho LEE ,  Moonyoung JEONG

IPC: H10B12/00

Abstract: Disclosed is a semiconductor device comprising: first and second gate structures adjacent to each other; a first active pillar and a second active pillar between the first gate structure and the second gate structure; a channel capping layer between the first active pillar and the second active pillar; and a bit-line structure in contact with the first active pillar, the second active pillar, and the channel capping layer, wherein each of the first and second gate structures includes: a first word line and a second word line that are spaced apart from each other; a gate dielectric layer in contact with the first word line and the second word line; and a gate capping layer in contact with the gate dielectric layer and spaced apart from the first word line and the second word line, and wherein the gate capping layer is in contact with the bit-line structure.

公开(公告)号：US20240422961A1

公开(公告)日：2024-12-19

申请号：US18640513

申请日：2024-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a plurality of word lines extending in a first horizontal direction, a plurality of back gate lines extending in the first horizontal direction and alternately arranged with the plurality of word lines in a second horizontal direction different from the first horizontal direction, a plurality of channel layers extending in a vertical direction between a word line and a back gate line adjacent to each other among the plurality of word lines and the plurality of back gate lines, to correspond to columns in the first horizontal direction, a plurality of bit lines extending in the second horizontal direction on the plurality of word lines, the plurality of back gate lines, and the plurality of channel layers and electrically connected to the plurality of channel layers, and a plurality of memory structures electrically connected to the plurality of channel layers.

公开(公告)号：US20240421223A1

公开(公告)日：2024-12-19

申请号：US18631839

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

IPC: H01L29/78 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first active pattern and a second active pattern on the bit line, a back gate electrode extending in a second direction perpendicular to the first direction across the bit line, and a word line extending in the second direction, wherein the first active pattern and the second active pattern have a minor symmetrical shape with respect to the back gate electrode when viewed in a third direction perpendicular to the first direction and the second direction.

公开(公告)号：US20240334677A1

公开(公告)日：2024-10-03

申请号：US18480389

申请日：2023-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho LEE ,  Moonyoung JEONG ,  Ilgweon KIM ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a bit line, first and second word lines spaced apart from each other on the bit line, a back gate electrode between the first and second word lines, a first active pattern between the first word line and the back gate electrode, a second active pattern between the second word line and the back gate electrode, contact patterns connected to the first and second active patterns, respectively, and a first gate insulating pattern between the first active pattern and the first word line and between the second active pattern and the second word line. A top surface of the first gate insulating pattern is located at substantially a same height as top surfaces of the first and second word lines. The first gate insulating pattern includes a high-k dielectric material.

公开(公告)号：US20230320066A1

公开(公告)日：2023-10-05

申请号：US17951379

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonyoung JEONG ,  Kiseok LEE ,  Hyungeun CHOI ,  Hyungjun NOH ,  Sangho LEE

IPC: H01L27/108

CPC classification number: H01L27/10805

Abstract: A semiconductor device may include a substrate including a memory cell region between a first connection region and a second connection region, gate electrodes extending in a first direction and including first pad regions having a step structure on the first connection region, back gate electrodes between the gate electrodes and extending in a direction opposite the first direction, vertical conductive patterns extending in a vertical direction and spaced apart from each other in the first direction on the memory cell region of the substrate, and active layers between the gate electrodes and the back gate electrodes on the memory cell region of the substrate. The active layers may extend in a second direction, intersecting the first direction, and may be electrically connected to the vertical conductive patterns. The back gate electrodes may include second pad regions having a step structure on the second connection region.