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公开(公告)号：US11561912B2
公开(公告)日：2023-01-24
申请号：US17321916
申请日：2021-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myungsub Shin , Sungho Seo , Kwanwoo Noh , Seongyong Jang , Haesung Jung
Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.
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12.发明授权公开(公告)号：US11150987B2
公开(公告)日：2021-10-19
申请号：US16891517
申请日：2020-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changkyu Seol , Hyejeong So , Kwanwoo Noh , Hongrak Son , Pilsang Yoon
Abstract: Channel selection information indicate positions of data bits of input data, positions of error correction code (ECC) parity bits for correcting errors in the input data, and positions of state shaping parity bits. The ECC parity bits and the state shaping parity bits are generated to cause a decrease in a quantity of memory cells, of the plurality of memory cells, in which at least one target state among a plurality of states is programmed. An alignment vector is generated based on aligning the data bits of the input data, the ECC parity bits, and the state shaping parity bits, based on the channel selection information. A codeword is generated based on simultaneously performing state shaping and ECC encoding with respect to the alignment vector. Write data are written in the nonvolatile memory device based on the codeword.
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公开(公告)号：US12130655B2
公开(公告)日：2024-10-29
申请号：US18508479
申请日：2023-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong , Dongwoo Nam , Myungsub Shin , Hyunkyu Jang
CPC classification number: G06F1/08 , G06F1/04 , G06F3/0632 , G06F3/0658 , G06F3/0679 , G06F13/4291 , G11C7/22 , G11C16/32 , H04L7/0004 , H04L7/0008
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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公开(公告)号：US12038857B2
公开(公告)日：2024-07-16
申请号：US18446670
申请日：2023-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeongsu Kim , Kwanwoo Noh , Sungho Seo , Yongwoo Jeong
CPC classification number: G06F13/1668 , G06F1/12 , G06F13/4027 , H04L1/0002 , H04L7/0008
Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.
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Patent Agency Ranking
公开(公告)号：US12019871B2
公开(公告)日：2024-06-25
申请号：US17865621
申请日：2022-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsuk Ra , Hanbyeul Na , Kwanwoo Noh , Mankeun Seo , Hong Rak Son , Jae Hun Jang
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0655 , G06F3/0679
Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.
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公开(公告)号：US11914531B2
公开(公告)日：2024-02-27
申请号：US18064062
申请日：2022-12-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myungsub Shin , Sungho Seo , Kwanwoo Noh , Seongyong Jang , Haesung Jung
CPC classification number: G06F13/1673 , G06F13/18
Abstract: A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.
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公开(公告)号：US11874695B2
公开(公告)日：2024-01-16
申请号：US18064002
申请日：2022-12-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong , Dongwoo Nam , Myungsub Shin , Hyunkyu Jang
CPC classification number: G06F1/08 , G06F1/04 , G06F3/0632 , G06F3/0658 , G06F3/0679 , G06F13/4291 , G11C7/22 , G11C16/32 , H04L7/0004 , H04L7/0008
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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公开(公告)号：US11782853B2
公开(公告)日：2023-10-10
申请号：US17467929
申请日：2021-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeongsu Kim , Kwanwoo Noh , Sungho Seo , Yongwoo Jeong
CPC classification number: G06F13/1668 , G06F1/12 , G06F13/4027 , H04L1/0002 , H04L7/0008
Abstract: A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.
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公开(公告)号：US11561571B2
公开(公告)日：2023-01-24
申请号：US17179830
申请日：2021-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong , Dongwoo Nam , Myungsub Shin , Hyunkyu Jang
Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.
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